Cypress Semiconductor EZ-Host CY7C67300 User Manual

PRELIMINARYCY7C67300Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600Document #: 38-08015 Rev. *D Revis

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 10 of 1201.0 INTRODUCTIONEZ-Host™ (CY7C67300) is Cypress Semiconductor’s first full-speed, low-

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 100 of 1207.14.5 PWM Cycle Count Register [0xC0FA] [R/W] Figure 7-93. PWM Cycle Count RegisterRe

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 101 of 1208.0 Pin Diagram 9.0 Pin DescriptionsTable 9-1. Pin Descriptions Pin Name Type Desc

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 102 of 12072 D10/SCK I/O D10: External Memory Data BusSCK: SPI SCK73 D9/nSSI I/O D9: External Me

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 103 of 12043 GPIO27/RX I/O GPIO27: General Purpose I/ORX: UART RX (Data is received on this pin)

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 104 of 12065 GPIO9/D9/nSSI I/O GPIO9: General Purpose I/OD9: D9 for HPI or IDEnSSI: SPI nSSI66 G

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 105 of 12010.0 Absolute Maximum RatingsThis section lists the absolute maximum ratings. Stresse

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 106 of 12013.0 DC Characteristics Table 13-1. DC CharacteristicsParameter Description Condit

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 107 of 12013.1 USB TransceiverUSB 2.0-certified in full- and low-speed modes.14.0 AC Timing Cha

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 108 of 12014.2 Clock Timing Note:13.vXINH is required to be 3.0 V to obtain an internal 50/50 d

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 109 of 12014.3 SRAM Read Cycle Notes:14. 0 wait state cycle.15. tAC External SRAM access time =

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 11 of 1202.0 Typical ApplicationsEZ-Host is a very powerful and flexible dual role USB controll

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 110 of 12014.4 SRAM Write Cycle Note:16. tWPW The write pulse width = 18.8 ns min. for zero and

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 111 of 12014.5 I2C EEPROM Timing Parameter Description Min. Typical Max. UnitfSCLClock Frequenc

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 112 of 12014.6 HPI (Host Port Interface) Write Cycle Timing Note:17. T = system clock period = 1

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 113 of 12014.7 HPI (Host Port Interface) Read Cycle Timing Parameter Description Min. Typical Ma

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 114 of 12014.8 IDE TimingThe IDE interface supports PIO mode 0-4 as specified in the Information

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 115 of 12014.12 Hardware CTS/RTS HandshaketCTSsetup: HSS_CTS set-up time before HSS_RTS = 1.

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 116 of 120R/W 0xC00E Interrupt Enable Reserved OTG InterruptEnableSPI InterruptEnableReserved Ho

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 117 of 120R/W 0xC0840xC0A4Host n Count Reserved Port Select Reserved Count... 0000 0000...Count

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 118 of 120R/W 0xC0B0 Device 2 Status Reserved SOF/EOPTimeoutInterrupt EnableWakeInterruptFlagSOF

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 119 of 120© Cypress Semiconductor Corporation, 2003. The information contained herein is subject

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 12 of 120 Notes:1. Default interface location.2. Alternate interface location.Table 4-1. Interf

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 120 of 120Document History PageDocument Title: CY7C67300 EZ-Host™ Programmable Embedded USB Host

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 13 of 1204.1 USB InterfaceEZ-Host has two built-in Host/Peripheral SIEs and four USB transceiver

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 14 of 1204.1.2 USB Pins.4.2 OTG InterfaceEZ-Host has one USB port that is compatible with the US

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 15 of 1204.3.3 Program Memory Hole DescriptionCode residing in the 0xC000-0xC0FF address space i

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 16 of 1204.3.5 External Memory Interface Block Diagrams[3] Note:3. Address lines do not map di

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 17 of 1204.4 General Purpose I/O Interface (GPIO)EZ-Host has up to 32 GPIO signals available. Se

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 18 of 1204.6.2 I2C EEPROM Pins. 4.7 Serial Peripheral InterfaceEZ-Host provides a SPI interface

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 19 of 1204.8.1 HSS Features• 8 bits, no parity code• Programmable baud rate from 9600 baud to 2

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 2 of 120TABLE OF CONTENTS1.0 INTRODUCTION ...

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 20 of 120speed connection to a host processor. Complete control of EZ-Host can be accomplished t

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 21 of 120The two HPI address pins are used to address one of four possible HPI port registers as

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 22 of 1204.11.2 IDE Pins 4.11.3 Charge Pump InterfaceVBUS for the USB OTG port can be produced

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 23 of 120Component details:• D1 and D2: Schottky diodes with a current rating greater than 60 mA

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 24 of 120Component details:• L1: Inductor with inductance of 10 uH and a current rating of at le

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 25 of 1204.11.7 Booster Pins.4.11.8 Crystal InterfaceThe recommended crystal circuit to be used

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 26 of 1204.12 Operational Modes4.12.1 Coprocessor ModeEZ-Host can act as a coprocessor to an ext

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 27 of 1205.0 Power Savings and Reset Description5.1 Power Savings Mode DescriptionEZ-Host has o

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 28 of 1206.0 Memory Map6.1 MappingThe EZ-Host has 64K bytes of total addressable memory contain

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 29 of 120 HW INT’sSW INT’s0x00000x0100Primary RegistersSwap Registers0x0144USB Registers0x0200R

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 3 of 120TABLE OF CONTENTS (continued)4.11.4 Charge Pump Features ...

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 30 of 1207.0 Registers7.1 Processor Control RegistersThere are nine registers dedicated to gene

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 31 of 120Carry Flag (Bit 1)The Carry Flag bit indicates if an arithmetic operation resulted in a

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 32 of 1207.1.3 Hardware Revision Register [0xC004] [R] Register DescriptionThe Hardware Revisi

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 33 of 120ReservedAll reserved bits should be written as ‘0’.7.1.5 Power Control Register [0xC00A

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 34 of 120OTG Wake Enable (Bit 11)The OTG Wake Enable bit enables or disables a wake-up condition

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 35 of 1207.1.6 Interrupt Enable Register [0xC00E] [R/W] Figure 7-7. Interrupt Enable RegisterRe

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 36 of 120Out Mailbox Interrupt Enable (Bit 5)The Out Mailbox Interrupt Enable bit enables or dis

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 37 of 1207.1.8 USB Diagnostic Register [0xC03C] [R/W] Figure 7-9. USB Diagnostic RegisterRegis

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 38 of 120Force Select (Bits [2:0])The Force Select field bit selects several different test cond

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 39 of 120Monitor Enable (Bit 0)The Monitor Enable bit enables or disables monitor mode. In monit

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 4 of 120TABLE OF CONTENTS (continued)7.5.9 Host n Status Register [R/W] ...

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 40 of 1207.2.2 External Memory Control Register [0xC03A] [R/W] Figure 7-13. External Memory Co

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 41 of 1207.3 Timer RegistersThere are three registers dedicated to timer operations. Each of the

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 42 of 120Reset Strobe (Bit 0)The Reset Strobe is a write-only bit that resets the Watchdog timer

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 43 of 120Register DescriptionThe USB n Control Register is used in both host and device mode. It

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 44 of 1201: Enable pull-up/pull-down resistors.0: Disable pull-up/pull-down resistorsPort B Forc

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 45 of 1207.5 USB Host Only RegistersThere are twelve sets of dedicated registers for USB host on

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 46 of 120Sync Enable (Bit 5)The Sync Enable bit will synchronize the transfer with the SOF packe

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 47 of 120Register DescriptionThe Host n Count Register is used to hold the number of bytes (pack

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 48 of 120Stall Flag (Bit 7)The Stall Flag bit indicates that the peripheral device replied with

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 49 of 120Register DescriptionThe Host n PID Register is a write-only register that provides the

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 5 of 120TABLE OF CONTENTS (continued)7.12.7 SPI CRC Value Register [0xC0D4] [R/W] ...

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 50 of 120ReservedAll reserved bits should be written as ‘0’.7.5.7 Host n Device Address Register

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 51 of 120VBUS Interrupt Enable (Bit 15)The VBUS Interrupt Enable bit will enable or disable the

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 52 of 1207.5.9 Host n Status Register [R/W]• Host 1 Status Register 0xC090.• Host 2 Status Regis

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 53 of 120Port A Connect Change Interrupt Flag (Bit 4)The Port A Connect Change Interrupt Flag bi

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 54 of 1207.5.11 Host n SOF/EOP Counter Register [R]• Host 1 SOF/EOP Counter Register 0xC094• Hos

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 55 of 120 7.6.1 Device n Endpoint n Control Register [R/W]• Device n Endpoint 0 Control Register

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 56 of 120Stall Enable (Bit 5)The Stall Enable bit will send a Stall in response to the next requ

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 57 of 120 Figure 7-34. Device n Endpoint n Address RegisterRegister DescriptionThe Device n Endp

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 58 of 120• Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6]• Device n End

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 59 of 120NAK Flag (Bit 6)The NAK Flag bit indicates that a NAK packet was sent to the host. 1: N

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 6 of 120LIST OF FIGURESFigure 1-1. Block Diagram ...

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 60 of 120 Figure 7-37. Device n Endpoint n Count Result RegisterRegister DescriptionThe Device n

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 61 of 120 Figure 7-39. Device n Interrupt Enable RegisterRegister DescriptionThe Device n Inter

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 62 of 120EP6 Interrupt Enable (Bit 6)The EP6 Interrupt Enable bit will enable or disable endpoin

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 63 of 120ReservedAll reserved bits should be written as ‘0’.7.6.8 Device n Address Register [W]•

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 64 of 120ID Interrupt Flag (Bit 14)The ID Interrupt Flag bit indicates the status of the OTG ID

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 65 of 120EP2 Interrupt Flag (Bit 2)The EP2 Interrupt Flag bit indicates if the endpoint two (EP2

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 66 of 120Frame (Bits [10:0])The Frame field contains the frame number from the last received SOF

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 67 of 120Register DescriptionThe OTG Control Register allows control and monitoring over the OTG

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 68 of 120VBUS Valid Flag (Bit 0)The VBUS Valid Flag bit indicates whether OTG VBus is greater th

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 69 of 120SAS Enable (Bit 11)The SAS Enable bit, when in SPI mode, will reroute the SPI port SPI_

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 7 of 120LIST OF FIGURES (continued)Figure 7-39. Device n Interrupt Enable Register ...

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 70 of 120Interrupt 0 Polarity Select (Bit 1)The Interrupt 0 Polarity Select bit selects the pola

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 71 of 120Data (Bits [15:0])The Data field[15:0] contains the voltage values on the corresponding

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 72 of 120Register DescriptionThe IDE Mode Register allows the selection of IDE PIO Modes 0, 1, 2

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 73 of 1207.9.3 IDE Stop Address Register [0xC04C] [R/W] Figure 7-54. IDE Stop Address RegisterR

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 74 of 120Done Flag (Bit 1)The Done Flag bit is automatically set to ‘1’ by hardware when a block

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 75 of 1207.10.1 HSS Control Register [0xC070] [R/W] Figure 7-57. HSS Control RegisterRegister D

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 76 of 120XOFF Enable (Bit 11)The XOFF Enable bit enables or disables XON/XOFF software handshaki

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 77 of 120Receive Packet Ready Flag (Bit 1)The Receive Packet Ready Flag bit is a read only bit t

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 78 of 120ReservedAll reserved bits should be written as ‘0’.7.10.4 HSS Data Register [0xC076] [R

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 79 of 1207.10.6 HSS Receive Counter Register [0xC07A] [R/W] Figure 7-62. HSS Receive Counter Re

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 8 of 120LIST OF FIGURES (continued)Figure 7-88. PWM Registers ...

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 80 of 1207.10.8 HSS Transmit Counter Register [0xC07E] [R/W] Figure 7-64. HSS Transmit Counter

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 81 of 120When the program counter matches the Breakpoint Address, the INT127 interrupt will trig

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 82 of 120SOF/EOP1 to CPU Enable (Bit 10)The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1 inter

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 83 of 1207.11.3 SIEXmsg Register [W]• SIE1msg Register 0x0144• SIE2msg Register 0x0148 Figure 7

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 84 of 1207.11.5 HPI Status Port [] [HPI: R] Figure 7-70. HPI Status PortRegister DescriptionThe

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 85 of 120Resume1 Flag (Bit 6)The Resume1 Flag bit is a read-only bit that indicates if a USB res

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 86 of 1207.12.1 SPI Configuration Register [0xC0C8] [R/W] Figure 7-72. SPI Configuration Regis

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 87 of 120Master Active Enable (Bit 7)The Master Active Enable bit is a read only bit that indica

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 88 of 120Register DescriptionThe SPI Control Register controls the SPI port. Fields apply to bot

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 89 of 120Transmit Bit Length (Bits [5:3])The Transmit Bit Length field indicates the number of b

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 9 of 120LIST OF TABLESTable 4-1. Interface Options for GPIO Pins ...

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 90 of 1207.12.4 SPI Status Register [0xC0CE] [R] Figure 7-75. SPI Status RegisterRegister Descr

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 91 of 120Transfer Interrupt Clear (Bit 0)The Transfer Interrupt Clear bit is a write-only bit th

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 92 of 120Zero in CRC (Bit 9)The Zero in CRC bit is a read-only bit that indicates if the CRC val

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 93 of 1207.12.9 SPI Transmit Address Register [0xC0D8] [R/W] Figure 7-80. SPI Transmit Address R

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 94 of 120Register DescriptionThe SPI Receive Address Register is issued as the base address for

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 95 of 120Scale Select (Bit 4)The Scale Select bit acts as a prescaler that will divide the baud

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 96 of 1201: Transmit buffer empty and ready for a new byte of data0: Transmit buffer is not empt

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 97 of 1207.14.1 PWM Control Register [0xC0E6] [R/W] Figure 7-89. PWM Control RegisterRegister D

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 98 of 120The PWM 1 Polarity Select bit selects the polarity for PWM 1.1: Sets the polarity to ac

CY7C67300PRELIMINARYDocument #: 38-08015 Rev. *D Page 99 of 120• PWM 2 Start Register 0xC0F2• PWM 3 Start Register 0xC0F6 Figure 7-91. PWM n Start Re