Cypress Semiconductor EZ-Host CY7C67300 User Manual download pdf (Page 75)

CY7C6730

PRELIMINARY

Document #: 38-08015 Rev. *D Page 75 of 120

7.10.1 HSS Control Register [0xC070] [R/W]

Figure 7-57. HSS Control Register

The HSS Control Register provides high-level status and control over the HSS port.

HSS Enable (Bit 15)

The HSS Enable bit enables or disables HSS operation.

1: Enables HSS operation

0: Disables HSS operation

RTS Polarity Select (Bit 14)

The RTS Polarity Select bit selects the polarity of RTS.

1: RTS is true when LOW

0: RTS is true when HIGH

CTS Polarity Select (Bit 13)

The CTS Polarity Select bit selects the polarity of CTS.

1: CTS is true when LOW

0: CTS is true when HIGH

XOFF (Bit 12)

The XOFF bit is a read-only bit that indicates if an XOFF has been received. This bit will automatically clear when an XON has

been received.

1: XOFF received

0: XON received

HSS Control Register 0xC070 R/W

HSS Baud Rate Register 0xC072 R/W

HSS Transmit Gap Register 0xC074 R/W

HSS Data Register 0xC076 R/W

HSS Receive Address Register 0xC078 R/W

HSS Receive Length Register 0xC07A R/W

HSS Transmit Address Register 0xC07C R/W

HSS Transmit Length Register 0xC07E R/W

Figure 7-56. HSS Registers

Bit # 15 14 13 12 11 10 9 8

Field HSS

Enable

RTS

Polarity

Select

CTS

Polarity

Select

XOFF XOFF

Enable

CTS

Enable

Receive

Interrupt

Enable

Done

Interrupt

Enable

Read/Write R/W R/W R/W R R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0

Field Transmit

Done Interrupt

Enable

Receive

Done Interrupt

Enable

One

Stop Bit

Transmit

Ready

Packet

Mode

Select

Receive

Overflow

Flag

Receive

Packet Ready

Flag

Receive

Ready

Flag

Read/Write R/W R/W R/W R R/W R/W R R

Default 0 0 0 0 0 0 0 0

1 2 ... 70 71 72 73 74 75 76 77 78 79 80 ... 119 120

Comments to this Manuals

No comments

Cypress Semiconductor EZ-Host CY7C67300 User Manual Page 75

Comments to this Manuals

Related products and manuals for Motherboards Cypress Semiconductor EZ-Host CY7C67300