CY7C6730
PRELIMINARY
Document #: 38-08015 Rev. *D Page 33 of 120
Reserved
All reserved bits should be written as ‘0’.
7.1.5 Power Control Register [0xC00A] [R/W]
Figure 7-6. Power Control Register
Register Description
The Power Control Register controls the power-down and wake-up options. Either the sleep mode or the halt mode options can
be selected. All other writable bits in this register can be used as a wake-up source while in sleep mode.
Host/Device 2B Wake Enable (Bit 15)
The Host/Device 2B Wake Enable bit enables or disables a wakeup condition to occur on a Host/Device 2B transition. This wake
up from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wake-up on Host/Device 2B transition.
0: Disable wake-up on Host/Device 2B transition.
Host/Device 2A Wake Enable (Bit 14)
The Host/Device 2A Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 2A transition. This wake
up from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wake-up on Host/Device 2A transition.
0: Disable wake-up on Host/Device 2A transition.
Host/Device 1B Wake Enable (Bit 13)
The Host/Device 1B Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 1B transition. This wake
up from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wake-up on Host/Device 1B transition.
0: Disable wake-up on Host/Device 1B transition.
Host/Device 1A Wake Enable (Bit 12)
The Host/Device 1A Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 1A transition. This wake
up from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wake-up on Host/Device 1A transition.
0: Disable wake-up on Host/Device 1A transition.
1100 48 MHz/13
1101 48 MHz/14
1110 48 MHz/15
1111 48 MHz/16
Bit # 15 14 13 12 11 10 9 8
Field Host/Device 2B
Wake
Enable
Host/Device 2A
Wake
Enable
Host/Device 1B
Wake
Enable
Host/Device 1A
Wake
Enable
OTG
Wake
Enable
Reserved HSS
Wake
Enable
SPI
Wake
Enable
Read/Write R/W R/W R/W R/W R/W - R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field HPI
Wake
Enable
Reserved GPI
Wake
Enable
Reserved Boost 3V
OK
Sleep
Enable
Halt
Enable
Read/Write R/W - - R/W - R R/W R/W
Default 0 0 0 0 0 0 0 0
Table 7-2. CPU Speed Definition (continued)
(76 pages)
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