Cypress Semiconductor EZ-Host CY7C67300 User Manual Page 38

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CY7C6730
0
PRELIMINARY
Document #: 38-08015 Rev. *D Page 38 of 120
Force Select (Bits [2:0])
The Force Select field bit selects several different test condition states on the data lines (D+/D–). Please refer to Table 7-3 for
details.
Reserved
All reserved bits should be written as ‘0’.
7.1.9 Memory Diagnostic Register [0xC03E] [W]
Figure 7-10. Memory Diagnostic Register
Register Description
The Memory Diagnostic Register provides control of diagnostic modes.
Memory Arbitration Select (Bits[10:8])
The Memory Arbitration Select field is defined in Table 7-4.
Table 7-3. Force Select Definition
Force Select [2:0] Data Line State
1xx Assert SE0
01x Toggle JK
001 Assert J
000 Assert K
Bit # 15 14 13 12 11 10 9 8
Field Reserved Memory
Arbitration
Select
Read/Write - - - - - W W W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field Reserved Monitor
Enable
Read/Write - - - - - - - W
Default 0 0 0 0 0 0 0 0
Table 7-4. Memory Arbitration Select
Memory Arbitration
Select [3:0] Memory Arbitration Timing
111 1/8, 7 of every 8 cycles dead
110 2/8, 6 of every 8 cycles dead
101 3/8, 5 of every 8 cycles dead
100 4/8, 4 of every 8 cycles dead
011 5/8, 3 of every 8 cycles dead
010 6/8, 2 of every 8 cycles dead
001 7/8, 1 of every 8 cycles dead
000 8/8, all cycles available
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