Cypress Semiconductor EZ-Host CY7C67300 User Manual Page 87

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CY7C6730
0
PRELIMINARY
Document #: 38-08015 Rev. *D Page 87 of 120
Master Active Enable (Bit 7)
The Master Active Enable bit is a read only bit that indicates if the master state machine is active or idle. This field only applies
to master mode.
1: Master state machine is active
0: Master state machine is idle
Master Enable (Bit 6)
The Master Enable bit sets the SPI interface to master or slave. This bit is only writable when the Master Active Enable bit reads
‘0’, otherwise value will not change.
1: Master SPI interface
0: Slave SPI interface
SS Enable (Bit 5)
The SS Enable bit enables or disables the master SS output.
1: Enable master SS output
0: Disable master SS output (three-state master SS output, for single SS line in slave mode)
SS Delay Select (Bits [4:0])
When the SS Delay Select field is set to ‘00000’ this indicates manual mode. In manual mode SS is controlled by SS Manual bit
of the SPI Control Register. When the SS Delay Select field is set between00001 to11111, this value indicates the count in
half bit times of auto transfer delay for: SS low to SCK active, SCK inactive to SShigh, SS high time. This field only applies to
master mode.
7.12.2 SPI Control Register [0xC0CA] [R/W]
Figure 7-73. SPI Control Register
0101 2 MHz
0110 1.5 MHz
0111 1 MHz
1000 750 KHz
1001 500 KHz
1010 375 KHz
1011 250 KHz
1100 375 KHz
1101 250 KHz
1110 375 KHz
1111 250 KHz
Bit # 15 14 13 12 11 10 9 8
Field SCK
Strobe
FIFO
Init
Byte
Mode
Full Duplex SS
Manual
Read
Enable
Transmit
Ready
Receive
Data
Ready
Read/Write W W W R R R R R/W
Default 0 0 0 0 0 0 0 1
Bit # 7 6 5 4 3 2 1 0
Field Transmit
Empty
Receive
Full
Transmit Bit Length Receive Bit Length
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 0 0 0 0 0 0 0
Table 7-13. Scale Select Field Definition for SCK Frequency (continued)
Scale Select [12:9] SCK Frequency
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