Cypress Semiconductor EZ-Host CY7C67300 User Manual download pdf (Page 110)

CY7C6730

PRELIMINARY

Document #: 38-08015 Rev. *D Page 110 of 120

14.4 SRAM Write Cycle

Note:

16. t

WPW

The write pulse width = 18.8 ns min. for zero and one wait states. The write pulse = 18.8 ns + (n – 1)*T for wait states = n, n > 1, T = 48-MHz clock period.

Parameter Description Min. Typical Max. Unit

Write address valid to WE LOW 7 ns

CSW

CS LOW to WE LOW 7 ns

Data valid to WE HIGH 15 ns

WPW

[16]

WE pulse width 15 ns

Data hold from WE HIGH 4.5 ns

WE HIGH to CS HIGH 13 ns

Address

Dout

CSW

WPW

Data Valid

1 2 ... 105 106 107 108 109 110 111 112 113 114 115 ... 119 120

PRELIMINARY 1
CY7C6730 1
CY7C67300 101

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Cypress Semiconductor EZ-Host CY7C67300 User Manual Page 110

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