Cypress Semiconductor CY7C63413C User Manual

CY7C63413CCY7C63513CCY7C63613CLow-Speed High Input/Output1.5-Mbps USB ControllerCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 10 of 36I/O Register SummaryI/O registers are accessed via the I/O Read (IORD) and

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 11 of 36Figure 2. Clock Oscillator On-chip CircuitClockingThe XTALIN and XTALOUT a

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 12 of 36General Purpose I/O PortsPorts 0 to 2 provide 24 GPI/O pins that can be rea

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 13 of 36Figure 4. Watch Dog Reset (WDR)Port 3 has eight GPIO pins. Port 3 (8 bits)

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 14 of 36In “Resistive” mode, a 7-k pull-up resistor is conditionally enabled for a

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 15 of 36DAC PortFigure 5. Block Diagram of DAC PortThe DAC port provides the CY7C6

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 16 of 36Table 14. DAC Port Interrupt EnableAddr: 0x31 DAC Port Interrupt Enable D

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 17 of 36USB Serial Interface Engine (SIE)The SIE allows the microcontroller to comm

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 18 of 36The Bus Activity bit is a “sticky” bit that indicates if any non-idle USB e

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 19 of 36The ‘Acknowledge’ bit is set whenever the SIE engages in a transaction that

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 2 of 36The Cypress microcontrollers use an external 6-MHz ceramic resonator to prov

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 20 of 3612-bit Free-running TimerThe 12-bit timer provides two interrupts (128 s a

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 21 of 36Processor Status and Control RegisterThe “Run” (bit 0) is manipulated by th

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 22 of 36Interrupt VectorsThe Interrupt Vectors supported by the USB Controller are

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 23 of 36interrupt priority to different DAC pins and the DAC Interrupt Enable Regis

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 24 of 36 The response of the SIE can be summarized as follows:1. the SIE will only

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 25 of 36Table 28. Details of Modes for Differing Traffic Conditions End Point Mode

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 26 of 36End Point Mode PID Set End Point Mode3 2 1 0 token count buffer dval DTOG D

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 27 of 36Absolute Maximum RatingsStorage temperature ...

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 28 of 36Notes9. Functionality is guaranteed of the VCC (1) range, except USB transm

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 29 of 36Figure 8. .Clock TimingFigure 9. USB Data Signal TimingFigure 10. Receiv

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 3 of 36ContentsPin Configuration ...

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 30 of 36Figure 11. Differential to EOP Transition Skew and EOP WidthFigure 12. Di

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 31 of 36Ordering InformationOrdering CodeEPROM SizePackageNamePackage TypeOperating

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 32 of 36Die Pad LocationsTable 29. DIe Pad Locations (in microns)Pad # Pin Name X

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 33 of 36Package Diagrams Figure 13. 48-Pin Shrunk Small Outline Package51-85061 *D

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 34 of 36Figure 14. 24-Pin SOIC (.615X.300X.0932 inches)51-85025 *DNot Recommended

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 35 of 36AcronymsDocument ConventionsUnits of MeasureAcronym Description Acronym Des

Document #: 38-08027 Rev. *E Revised January 18, 2011 Page 36 of 36All products and company names mentioned in this document may be the trademarks o

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 4 of 36.Note1. CY7C63613C is not bonded out for all GPIO pins shown in Logic Block

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 5 of 36Programming Model14-bit Program Counter (PC)The 14-bit Program Counter (PC)

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 6 of 36PSP,A instruction. The PSP supports interrupt service under hardware control

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 7 of 36Instruction Set SummaryMNEMONIC operand opcode cycles MNEMONIC operand opcod

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 8 of 36Memory OrganizationProgram Memory OrganizationFigure 1. Program Memory Spac

CY7C63413CCY7C63513CCY7C63613CDocument #: 38-08027 Rev. *E Page 9 of 36Data Memory OrganizationThe CY7C63413C/513C/613C microcontrollers provide 25