CY7C6730
PRELIMINARY
Document #: 38-08015 Rev. *D Page 85 of 120
Resume1 Flag (Bit 6)
The Resume1 Flag bit is a read-only bit that indicates if a USB resume interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
SIE2msg (Bit 5)
The SIE2msg Flag bit is a read only bit that indicates if the CY7C67300 CPU has written to the SIE2msg register. This bit will
clear on an HPI read.
1: The SIE2msg register has been written by the CY7C67300 CPU
0: The SIE2msg register has not been written by the CY7C67300 CPU
SIE1msg (Bit 4)
The SIE1msg Flag bit is a read only bit that indicates if the CY7C67300 CPU has written to the SIE1msg register. This bit will
clear on an HPI read.
1: The SIE1msg register has been written by the CY7C67300 CPU
0: The SIE1msg register has not been written by the CY7C67300 CPU
Done2 Flag (Bit 3)
In host mode the Done2 Flag bit is a read-only bit that indicates if a host packet done interrupt occurs on Host 2. In device mode
this read-only bit indicates if an any of the endpoint interrupts occurs on Device 2. Firmware will need to determine which endpoint
interrupt occurred.
1: Interrupt triggered
0: Interrupt did not trigger
Done1 Flag (Bit 2)
In host mode the Done 1 Flag bit is a read-only bit that indicates if a host packet done interrupt occurs on Host 1. In device mode
this read-only bit indicates if an any of the endpoint interrupts occurs on Device 1. Firmware will need to determine which endpoint
interrupt occurred.
1: Interrupt triggered
0: Interrupt did not trigger
Reset1 Flag (Bit 1)
The Reset1 Flag bit is a read-only bit that indicates if a USB Reset interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
Mailbox Out Flag (Bit 0)
The Mailbox Out Flag bit is a read-only bit that indicates if a message is ready in the outgoing mailbox. This interrupt clears when
the external host reads from the HPI Mailbox Register.
1: Interrupt triggered
0: Interrupt did not trigger
7.12 SPI Registers
There are twelve registers dedicated to SPI operation. Each of these registers is covered in this section and summarized in
Figure 7-71.
Register Name Address R/W
SPI Configuration Register 0xC0C8 R/W
SPI Control Register 0xC0CA R/W
SPI Interrupt Enable Register 0xC0CC R/W
SPI Status Register 0xC0CE R
SPI Interrupt Clear Register 0xC0D0 W
SPI CRC Control Register 0xC0D2 R/W
Figure 7-71. SPI Registers
(76 pages)
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