Cypress Semiconductor CY7C63613C User Manual

CY7C63413CCY7C63513CCY7C63613CLow-Speed High Input/Output1.5-Mbps USB ControllerCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 10 of 37I/O Register SummaryI/O registers are accessed via the I/O Read (IORD)

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 11 of 37Figure 2. Clock Oscillator On-chip CircuitClockingThe XTALIN and XTALO

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 12 of 37General Purpose I/O PortsPorts 0 to 2 provide 24 GPI/O pins that can be

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 13 of 37Figure 4. Watch Dog Reset (WDR)Port 3 has eight GPIO pins. Port 3 (8 b

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 14 of 37In “Resistive” mode, a 7-kΩ pull-up resistor is conditionally enabled f

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 15 of 37DAC PortFigure 5. Block Diagram of DAC PortThe DAC port provides the C

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 16 of 37Table 14. DAC Port Interrupt EnableAddr: 0x31 DAC Port Interrupt Enabl

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 17 of 37USB Serial Interface Engine (SIE)The SIE allows the microcontroller to

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 18 of 37The Bus Activity bit is a “sticky” bit that indicates if any non-idle U

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 19 of 37The ‘Acknowledge’ bit is set whenever the SIE engages in a transaction

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 2 of 37The Cypress microcontrollers use an external 6-MHz ceramic resonator to

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 20 of 3712-bit Free-running TimerThe 12-bit timer provides two interrupts (128

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 21 of 37Processor Status and Control RegisterThe “Run” (bit 0) is manipulated b

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 22 of 37Interrupt VectorsThe Interrupt Vectors supported by the USB Controller

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 23 of 37interrupt priority to different DAC pins and the DAC Interrupt Enable R

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 24 of 37 The response of the SIE can be summarized as follows:1. the SIE will o

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 25 of 37Table 28. Details of Modes for Differing Traffic Conditions End Point

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 26 of 370 0 1 0 Out 2 UC valid 0 1 updates UC UC 1 UC 0 0 1 1 Stall yesEnd Poin

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 27 of 37Absolute Maximum RatingsStorage temperature ...

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 28 of 37Notes9. Functionality is guaranteed of the VCC (1) range, except USB tr

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 29 of 37Figure 8. .Clock TimingFigure 9. USB Data Signal TimingFigure 10. Re

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 3 of 37ContentsPin Configuration ...

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 30 of 37Figure 11. Differential to EOP Transition Skew and EOP WidthFigure 12.

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 31 of 37Ordering InformationOrdering CodeEPROM SizePackageNamePackage TypeOpera

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 32 of 37Die Pad LocationsTable 29. DIe Pad Locations (in microns)Pad # Pin Nam

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 33 of 37Package DiagramsFigure 13. 48-pin SSOP (300 Mils) Package Outline, 51-

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 34 of 37Figure 14. 24-pin SOIC (0.615 × 0.300 × 0.0932 Inches) Package Outline

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 35 of 37AcronymsDocument ConventionsUnits of MeasureAcronym Description Acronym

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 36 of 37Document History PageDocument Title: CY7C63413C/CY7C63513C/CY7C63613C,

Document Number: 38-08027 Rev. *G Revised March 21, 2014 Page 37 of 37All products and company names mentioned in this document may be the trademarks

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 4 of 37.Note1. CY7C63613C is not bonded out for all GPIO pins shown in Logic Bl

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 5 of 37Programming Model14-bit Program Counter (PC)The 14-bit Program Counter (

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 6 of 37PSP,A instruction. The PSP supports interrupt service under hardware con

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 7 of 37Instruction Set SummaryMNEMONIC operand opcode cycles MNEMONIC operand o

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 8 of 37Memory OrganizationProgram Memory OrganizationFigure 1. Program Memory

CY7C63413CCY7C63513CCY7C63613CDocument Number: 38-08027 Rev. *G Page 9 of 37Data Memory OrganizationThe CY7C63413C/513C/613C microcontrollers provid