Cypress Semiconductor EZ-Host CY7C67300 User Manual Page 74

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CY7C6730
0
PRELIMINARY
Document #: 38-08015 Rev. *D Page 74 of 120
Done Flag (Bit 1)
The Done Flag bit is automatically set to ‘1’ by hardware when a block transfer is complete. The CPU clears this bit by writing a
‘0’ to it. When IDE Interrupt Enable is set this bit generates the signal for the cpuide_intr interrupt.
1: Block transfer is complete
0: Clears IDE Done Flag
IDE Enable (Bit 0)
The IDE Enable bit will start a block transfer. It is reset to ‘0’ when the block transfer is complete
1: Start block transfer
0: Block transfer complete
Reserved
All reserved bits should be written as ‘0’.
7.9.5 IDE PIO Port Registers [0xC050 - 0xC06F] [R/W]
All IDE PIO Port Registers [0xC050 - 0xC06F] in Table 7-12 are defined in detail in the Information Technology-AT Attachment -
4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. In Table 7-12 below, the Address column
denotes the CY7C67300 register address for the corresponding ATA/ATAPI register. The IDE_nCS[1:0] field defines the ATA
interface CS addressing bits and the IDE_A[2:0] field define the ATA interface address bits. The combination of IDE_nCS and
IDE_A are the ATA interface register address.
7.10 HSS Registers
There are eight registers dedicated to HSS operation. Each of these registers are covered in this section and summarized in
Figure 7-56.
Table 7-12. IDE PIO Port Registers
Address ATA/ATAPI Register IDE_nCS[1:0] IDE_A[2:0]
0xC050 DATA Register ‘10’ ‘000’
0xC052 Read: Error Register
Write: Feature Register
‘10’ ‘001’
0xC054 Sector Count Register ‘10’ ‘010’
0xC056 Sector Number Register ‘10’ ‘011’
0xC058 Cylinder Low Register ‘10’ ‘100’
0xC05A Cylinder High Register ‘10’ ‘101’
0xC05C Device/Head Register ‘10’ ‘110’
0xC05E Read: Status Register
Write: Command Register
‘10’ 111’
0xC060 Not Defined ‘01’ ‘000’
0xC062 Not Defined ‘01’ ‘001’
0xC064 Not Defined ‘01’ ‘010’
0xC066 Not Defined ‘01’ ‘011’
0xC068 Not Defined ‘01’ ‘100’
0xC06A Not Defined ‘01’ ‘101’
0xC06C Read: Alternate Status Register
Write: Device Control Register
‘01’ ‘110’
0xC06E Not Defined ‘01’ ‘111’
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