Cypress Semiconductor EZ-Host CY7C67300 User Manual download pdf (Page 89)

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Transmit Bit Length (Bits [5:3])

The Transmit Bit Length field indicates the number of bits in the last transmitted byte or partial byte. If Transmit Bit Length is ‘000’

then the last transmitted byte is a full-byte transfer. If Transmit Bit Length is ‘001’ to ‘111’, then the value indicates the bit count

of the last transmitted partial byte.

Receive Bit Length (Bits [2:0])

The Receive Bit Length field indicates the number of bits in the last received byte or partial byte. If Receive Bit Length is ‘000’

then the last received byte is a full-byte transfer. If Receive Bit Length is ‘001’ to ‘111’, then the value indicates the bit count of

the last received partial byte.

7.12.3 SPI Interrupt Enable Register [0xC0CC] [R/W]

Figure 7-74. SPI Interrupt Enable Register

The SPI Interrupt Enable Register controls the SPI port.

Receive Interrupt Enable (Bit 2)

The Receive Interrupt Enable bit will enable or disable the byte mode receive interrupt (RxIntVal).

1: Enable byte mode receive interrupt

0: Disable byte mode receive interrupt

Transmit Interrupt Enable (Bit 1)

The Transmit Interrupt Enable bit will enable or disable the byte mode transmit interrupt (TxIntVal).

1: Enables byte mode transmit interrupt

0: Disables byte mode transmit interrupt

Transfer Interrupt Enable (Bit 0)

The Transfer Interrupt Enable bit will enable or disable the block mode interrupt (XfrBlkIntVal).

1: Enables block mode interrupt

0: Disables block mode interrupt

Reserved

All reserved bits should be written as ‘0’.

Bit # 15 14 13 12 11 10 9 8

Field Reserved...

Read/Write - - - - - - - -

Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0

Field ...Reserved Receive

Interrupt

Enable

Transmit

Interrupt

Enable

Transfer

Interrupt

Enable

Read/Write - - - - - R/W R/W R/W

Default 0 0 0 0 0 0 0 0

1 2 ... 84 85 86 87 88 89 90 91 92 93 94 ... 119 120

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Cypress Semiconductor EZ-Host CY7C67300 User Manual Page 89

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