CY7C6730
PRELIMINARY
Document #: 38-08015 Rev. *D Page 90 of 120
7.12.4 SPI Status Register [0xC0CE] [R]
Figure 7-75. SPI Status Register
Register Description
The SPI Status Register is a read-only register that provides status for the SPI port.
FIFO Error Flag (Bit 7)
The FIFO Error Flag bit is a read-only bit that indicates if a FIFO error occurred. When this bit is set to ‘1’ and the Transmit Empty
bit of the SPI Control Register is set to ‘1’, then a Tx FIFO underflow has occurred. Similarly, when set with the Receive Full bit
of the SPI Control Register, an Rx FIFO overflow has occured.This bit automatically clears when the SPI FIFO Init Enable bit of
the SPI Control register is set.
1: Indicates FIFO error
0: Indicates no FIFO error
Receive Interrupt Flag (Bit 2)
The Receive Interrupt Flag is a read-only bit that indicates a byte mode receive interrupt has triggered when set to ‘1’.
Transmit Interrupt Flag (Bit 1)
The Transmit Interrupt Flag is a read-only bit that indicates a byte mode transmit interrupt has triggered when set to ‘1’.
Transfer Interrupt Flag (Bit 0)
The Transfer Interrupt Flag is a read-only bit that indicates a block mode interrupt has triggered when set to ‘1’.
7.12.5 SPI Interrupt Clear Register [0xC0D0] [W]
Figure 7-76. SPI Interrupt Clear Register
Register Description
The SPI Interrupt Clear Register is a write-only register that allows the SPI Transmit and SPI Transfer Interrupts to be cleared.
Transmit Interrupt Clear (Bit 1)
The Transmit Interrupt Clear bit is a write-only bit that will clear the byte mode transmit interrupt when set to ‘1’. This bit is self
clearing.
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field FIFO Error
Flag
Reserved
Receive
Interrupt
Flag
Transmit
Interrupt
Flag
Transfer
Interrupt
Flag
Read/Write R - - - - R R R
Default 0 0 0 0 0 0 0 0
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field Reserved Transmit
Interrupt
Clear
Transfer
Interrupt
Clear
Read/Write - - - - - - W W
Default 0 0 0 0 0 0 0 0
(76 pages)
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