CY7C6730
PRELIMINARY
Document #: 38-08015 Rev. *D Page 81 of 120
When the program counter matches the Breakpoint Address, the INT127 interrupt will trigger. To clear this interrupt, a zero value
should be written to this register.
Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint address.
7.11.2 Interrupt Routing Register [0x0142] [R]
Figure 7-67. Interrupt Routing Register
Register Description
The Interrupt Routing Register allows the HPI port to take over some or all of the SIE interrupts that usually go to the on-chip
CPU. This register is read only by the CPU but is read/write by the HPI port. By setting the appropriate bit to ‘1’, the SIE interrupt
is routed to the HPI port to become the HPI_INTR signal and also readable in the HPI Status Register. The bits in this register
select where the interrupts are routed. The individual interrupt enable is handled in the SIE interrupt enable register.
VBUS to HPI Enable (Bit 15)
The VBUS to HPI Enable bit routes the OTG VBUS interrupt to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
ID to HPI Enable (Bit 14)
The ID to HPI Enable bit routes the OTG ID interrupt to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP2 to HPI Enable (Bit 13)
The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt to the HPI port.
1: Route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP2 to CPU Enable (Bit 12)
The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2 interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can be
routed to both the on-chip CPU and the HPI port the firmware must ensure only one of the two (CPU, HPI) resets the interrupt.
1: Route signal to CPU
0: Do not route signal to CPU
SOF/EOP1 to HPI Enable (Bit 11)
The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1 interrupt to the HPI port.
1: Route signal to HPI port
0: Do not route signal to HPI port
Bit # 15 14 13 12 11 10 9 8
Field VBUS to HPI
Enable
ID to HPI
Enable
SOF/EOP2 to
HPI Enable
SOF/EOP2 to
CPU Enable
SOF/EOP1 to
HPI Enable
SOF/EOP1 to
CPU Enable
Reset2 to HPI
Enable
HPI Swap 1
Enable
Read/Write - - - - - - - -
Default 0 0 0 1 0 1 0 0
Bit # 7 6 5 4 3 2 1 0
Field Resume2 to
HPI Enable
Resume1 to
HPI Enable
Reserved Done2 to HPI
Enable
Done1 to HPI
Enable
Reset1 to HPI
Enable
HPI Swap 0
Enable
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
(76 pages)
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