Cypress Semiconductor EZ-Host CY7C67300 User Manual download pdf (Page 94)

CY7C6730

PRELIMINARY

Document #: 38-08015 Rev. *D Page 94 of 120

The SPI Receive Address Register is issued as the base address for the SPI Receive DMA.

Address (Bits [15:0])

The Address field sets the base address for the SPI receive DMA.

7.12.12 SPI Receive Count Register [0xC0DE] [R/W]

Figure 7-83. SPI Receive Count Register

The SPI Receive Count Register designates the block byte length for the SPI receive DMA transfer.

Count (Bits [10:0])

The Count field sets the count for the SPI receive DMA transfer.

Reserved

All reserved bits should be written as ‘0’.

7.13 UART Registers

There are three registers dedicated to UART operation. Each of these registers is covered in this section and summarized in

Figure 7-84.

7.13.1 UART Control Register [0xC0E0] [R/W]

Figure 7-85. UART Control Register

The UART Control Register enables or disables the UART allowing GPIO28 (UART_TXD) and GPIO27 (UART_RXD) to be freed

up for general use. This register must also be written to set the baud rate which is based on a 48-MHz clock.

Bit # 15 14 13 12 11 10 9 8

Field Reserved Count...

Read/Write - - - - - R/W R/W R/W

Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0

Field ...Count

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0

UART Control Register 0xC0E0 R/W

UART Status Register 0xC0E2 R

UART Data Register 0xC0E4 R/W

Figure 7-84. UART Registers

Bit # 15 14 13 12 11 10 9 8

Field Reserved...

Read/Write - - - - - - - -

Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0

Field ...Reserved Scale Select Baud Select UART Enable

Read/Write - - - R/W R/W R/W R/W R/W

Default 0 0 0 0 0 1 1 1

1 2 ... 89 90 91 92 93 94 95 96 97 98 99 ... 119 120

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Cypress Semiconductor EZ-Host CY7C67300 User Manual Page 94