Cypress Semiconductor EZ-Host CY7C67300 User Manual Page 42

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CY7C6730
0
PRELIMINARY
Document #: 38-08015 Rev. *D Page 42 of 120
Reset Strobe (Bit 0)
The Reset Strobe is a write-only bit that resets the Watchdog timer count. It must be set to ‘1’ before the count expires to avoid
a Watchdog trigger
1: Reset Count
Reserved
All reserved bits should be written as ‘0’.
7.3.2 Timer n Register [R/W]
Timer 0 Register 0xC010.
Timer 1 Register 0xC012.
Figure 7-16. Timer n Register
Register Description
The Timer n Register sets the Timer n count. Both Timer 0 and Timer 1 decrement by one every 1-µs clock tick. Each can provide
an interrupt to the CPU when the timer reaches zero.
Count (Bits [15:0])
The Count field sets the Timer count.
7.4 General USB Registers
There is one set of register dedicated to general USB control. This set consists of two identical registers, one for Host/Device
Port 1 and one for Host/Device Port 2. This register set has functions for both USB host and USB peripheral options and is covered
in this section and summarized in Figure 7-8. USB Host only registers are covered in section 4.5, and USB device-only registers
are covered in section 7.2.
7.4.1 USB n Control Register [R/W]
USB 1 Control Register 0xC08A.
USB 2 Control Register 0xC0AA.
Figure 7-18. USB n Control Register
Bit # 15 14 13 12 11 10 9 8
Field Count...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1
Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1
Register Name Address (SIE1 / SIE2) R/W
USB n Control Register 0xC08A / 0xC0AA R/W
Figure 7-17. General USB Registers
Bit # 15 14 13 12 11 10 9 8
Field Port B
D+
Status
Port B
D–
Status
Port A
D+
Status
Port A
D–
Status
LOB LOA Mode
Select
Port B
Resistors
Enable
Read/Write R R R R R/W R/W R/W R/W
Default X X X X 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field Port A
Resistors
Enable
Port B
Force D±
State
Port A
Force D±
State
Suspend
Enable
Port B
SOF/EOP
Enable
Port A
SOF/EOP
Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
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