Cypress Semiconductor EZ-Host CY7C67300 User Manual Page 68

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CY7C6730
0
PRELIMINARY
Document #: 38-08015 Rev. *D Page 68 of 120
VBUS Valid Flag (Bit 0)
The VBUS Valid Flag bit indicates whether OTG VBus is greater then 4.4V. After turning on VBUS, firmware should wait at least
10 µs before this reading this bit.
1: OTG VBus is greater then 4.4V
0: OTG VBus is less then 4.4V
Reserved
All reserved bits should bit written as ‘0’.
7.8 GPIO Registers
There are seven registers dedicated for GPIO operations. These seven registers are covered in this section and summarized in
Figure 7-46.
7.8.1 GPIO Control Register [0xC006] [R/W]
Figure 7-47. GPIO Control Register
Register Description
The GPIO Control Register configures the GPIO pins for various interface options. It also controls the polarity of the GPIO interrupt
on IRQ1 (GPIO25) and IRQ0 (GPIO24).
Write Protect Enable (Bit 15)
The Write Protect Enable bit enables or disables the GPIO write protect. When Write Protect is enabled, the GPIO Mode Select
[10:8] field read-only until a chip reset.
1: Enable Write Protect
0: Disable Write Protect
UD (Bit 14)
The UD bit routes the Host/Device 1A Port’s transmitter enable status to GPIO[30]. This is for use with an external ESD protection
circuit when needed.
1: Route the signal to GPIO[30]
0: Do not route the signal to GPIO[30]
Register Name Address R/W
GPIO Control Register 0xC006 R/W
GPIO0 Output Data Register 0xC01E R/W
GPIO0 Input Data Register 0xC020 R
GPIO0 Direction Register 0xC022 R/W
GPIO1 Output Data Register 0xC024 R/W
GPIO1 Input Data Register 0xC026 R
GPIO1 Direction Register 0xC028 R/W
Figure 7-46. GPIO Registers
Bit # 15 14 13 12 11 10 9 8
Field Write Protect
Enable
UD
Reserved
SAS
Enable
Mode
Select
Read/Write R/W R/W - - R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field HSS
Enable
HSS XD
Enable
SPI
Enable
SPI XD
Enable
Interrupt 1
Polarity Select
Interrupt 1
Enable
Interrupt 0
Polarity Select
Interrupt 0
Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
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