CY7C6730
PRELIMINARY
Document #: 38-08015 Rev. *D Page 34 of 120
OTG Wake Enable (Bit 11)
The OTG Wake Enable bit enables or disables a wake-up condition to occur on either an OTG VBUS_Valid or OTG ID transition
(IRQ20).
1: Enable wake-up on OTG VBUS valid or OTG ID transition.
0: Disable wake-up on OTG VBUS valid or OTG ID transition.
HSS Wake Enable (Bit 9)
The HSS Wake Enable bit enables or disables a wake-up condition to occur on an HSS Rx serial input transition. The processor
may take several hundreds of microseconds before being operational after wake-up. Therefore, the incoming data byte that
causes the wake-up will be discarded.
1: Enable wake-up on HSS Rx serial input transition.
0: Disable wake-up on HSS Rx serial input transition.
SPI Wake Enable (Bit 8)
The SPI Wake Enable bit enables or disables a wake-up condition to occur on a falling SPI_nSS input transition. The processor
may take several hundreds of microseconds before being operational after wake-up. Therefore, the incoming data byte that
causes the wake-up will be discarded.
1: Enable wake-up on falling SPI nSS input transition.
0: Disable SPI_nSS interrupt.
HPI Wake Enable (Bit 7)
The HPI Wake Enable bit enables or disables a wake-up condition to occur on an HPI interface read.
1: Enable wake-up on HPI interface read.
0: Disable wake-up on HPI interface read.
GPI Wake Enable (Bit 4)
The GPI Wake Enable bit enables or disables a wake-up condition to occur on a GPIO(25:24) transition.
1: Enable wake-up on GPIO(25:24) transition.
0: Disable wake-up on GPIO(25:24) transition.
Boost 3V OK (Bit 2)
The Boost 3V OK bit is a read only bit that returns the status of the OTG Boost circuit.
1: Boost circuit not ok and internal voltage rails are below 3.0V.
0: Boost circuit ok and internal voltage rails are at or above 3.0V
Sleep Enable (Bit 1)
Setting this bit to ‘1’ will immediately initiate SLEEP mode. While in SLEEP mode, the entire chip is paused, achieving the lowest
standby power state. All operations are paused, the internal clock is stopped, the booster circuit and OTG VBUS charge pump
are all powered down, and the USB transceivers are powered down. All counters and timers are paused but will retain their values;
enabled PWM outputs freeze in their current states. SLEEP mode exits by any activity selected in this register. When SLEEP
mode ends, instruction execution will resume within 0.5 ms.
1: Enable Sleep mode.
0: No function.
Halt Enable (Bit 0)
Setting this bit to ‘1’ will immediately initiate HALT mode. While in HALT mode, only the CPU is stopped. The internal clock still
runs and all peripherals still operate, including the USB engines. The power saving using HALT in most cases will be minimal,
but in applications that are very CPU intensive the incremental savings may provide some benefit.
The HALT state is exited when any enabled interrupt is triggered. Upon exiting the HALT state, one or two instructions immediately
following the HALT instruction may be executed before the waking interrupt is serviced (you may want to follow the HALT
instruction with two NOPs).
1: Enable Halt mode.
0: No function.
Reserved
All reserved bits should be written as ‘0’.
(76 pages)
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