Cypress Semiconductor EZ-Host CY7C67300 User Manual download pdf (Page 116)

CY7C6730

PRELIMINARY

Document #: 38-08015 Rev. *D Page 116 of 120

R/W 0xC00E Interrupt Enable Reserved OTG Interrupt

Enable

SPI Interrupt

Enable

Reserved Host/Device 2

Interrupt

Enable

Host/Device 1

Interrupt

Enable

0000 0000

HSS

Interrupt

Enable

In Mailbox

Interrupt

Enable

Out Mailbox

Interrupt

Enable

Reserved UART

Interrupt

Enable

GPIO

Interrupt

Enable

Timer 1

Interrupt

Enable

Timer 0

Interrupt

Enable

0001 0000

R/W 0xC098 OTG Control Reserved VBUS

Pullup

Enable

Receive

Disable

Charge Pump

Enable

VBUS

Discharge

Enable

D+

Pullup

Enable

D-

Pullup

Enable

0000 0000

D+ Pulldown

Enable

D- Pulldown

Enable

Reserved OTG Data

Status

VBUS Valid

Flag

0000 0xxx

R/W 0: 0xC010

1: 0xC012

Timer n Count... 1111 1111

...Count 1111 1111

R/W 0xC014 Breakpoint Address... 0000 0000

...Address 0000 0000

R/W 1: 0xC018

2: 0xC01A

Extended Page n Map Address... 0000 0000

...Address 0000 0000

R/W 0: 0xC01E

1: 0xC024

GPIO n Output Data Data... 0000 0000

...Data 0000 0000

R0: 0xC020

1: 0xC026

GPIO n Input Data Data... 0000 0000

...Data 0000 0000

R/W 0: 0xC022

1: 0xC028

GPIO n Direction Direction Select... 0000 0000

...Direction Select 0000 0000

R/W 0xC03A External Memory Control Reserved XRAM

Merge Enable

XROM

Merge Enable

XMEM

Width Select

XMEM

Wait Select

xxxx xxxx

XROM

Width Select

XROM

Wait Select

XRAM

Width Select

XRAM

Wait Select

xxxx xxxx

R/W 0xC03C USB Diagnostic Port 2B

Diagnostic

Enable

Port 2A

Diagnostic

Enable

Port 1B

Diagnostic

Enable

Port 1A

Diagnostic

Enable

Reserved... 0000 0000

...Reserved Pulldown

Enable

LS Pullup

Enable

FS Pullup

Enable

Reserved Force Select 0000 0000

W 0xC03E Memory Diagnostic Reserved Memory

Arbitration

Select

0000 0000

Reserved Monitor

Enable

0000 0000

R/W 0xC048 IDE Mode Reserved... 0000 0000

...Reserved Reserved Mode Select 0000 0000

R/W 0xC04A IDE Start Address Address... 0000 0000

... Address 0000 0000

R/W 0xC04C IDE Stop Address Address... 0000 0000

...Address 0000 0000

R/W 0xC04E IDE Control Reserved... 0000 0000

...Reserved Direction

Select

IDE Interrupt

Enable

Done

Flag

IDE

Enable

0000 0000

- 0xC050-

0xC06E

IDE PIO Port

R/W 0xC070 HSS Control HSS

Enable

RTS

Polarity

Select

CTS

Polarity

Select

XOFF XOFF

Enable

CTS

Enable

Receive

Interrupt

Enable

Done

Interrupt

Enable

0000 0000

Transmit Done

Interrupt Flag

Receive Done

Interrupt Flag

One

Stop Bit

Transmit

Ready

Packet Mode

Select

Receive

Overflow Flag

Receive Pack-

et Ready Flag

Receive

Ready Flag

0000 0000

R/W 0xC072 HSS Baud Rate Reserved HSS Baud... 0000 0000

...Baud 0001 0111

R/W 0xC074 HSS Transmit Gap Reserved 0000 0000

Transmit Gap Select 0000 1001

R/W 0xC076 HSS Data Reserved xxxx xxxx

Data xxxx xxxx

R/W 0xC078 HSS Receive Address Address... 0000 0000

...Address 0000 0000

R/W 0xC07A HSS Receive Counter Reserved Counter... 0000 0000

...Counter 0000 0000

R/W 0xC07C HSS Transmit Address Address.. 0000 0000

...Address 0000 0000

R/W 0xC07E HSS Transmit Counter Reserved Counter... 0000 0000

...Counter 0000 0000

R/W 0xC080

0xC0A0

Host n Control Reserved 0000 0000

Preamble

Enable

Sequence

Select

Sync

Enable

ISO

Enable

Reserved Arm

Enable

0000 0000

R/W 0xC082

0xC0A2

Host n Address Address... 0000 0000

...Address 0000 0000

Table 15-1. Register Summary (continued)

R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low

1 2 ... 111 112 113 114 115 116 117 118 119 120

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Cypress Semiconductor EZ-Host CY7C67300 User Manual Page 116

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