Cypress Semiconductor Perform CY7C1356C User Manual

PRELIMINARY256Kx36/512Kx18 Pipelined SRAM with NoBL™ Architecture CY7C1354V25CY7C1356V25 Cypress Semiconductor Corporation• 3901 North First Street •

CY7C1354V25CY7C1356V25PRELIMINARY10Write Cycle Description[1]Function (CY7C1354V25) WE BWSdBWScBWSbBWSaRead 1XXXXWrite - No bytes written 01111Write

CY7C1354V25CY7C1356V25PRELIMINARY11IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1354V25/56V25 incorporates a serial boundaryscan Test Access Port (

CY7C1354V25CY7C1356V25PRELIMINARY12SRAM does not implement the 1149.1 commands EXTEST orINTEST or the PRELOAD portion of SAMPLE / PRELOAD;rather it p

CY7C1354V25CY7C1356V25PRELIMINARY13TAP Controller State DiagramTEST-LOGICRESETTEST-LOGIC/IDLESELECTDR-SCANCAPTURE-DRSHIFT-DREXIT1-DRPAUSE-DREXIT2-DRU

CY7C1354V25CY7C1356V25PRELIMINARY14TAP Controller Block Diagram0012..293031Boundary Scan RegisterIdentification Register012...x012Instruction Regist

CY7C1354V25CY7C1356V25PRELIMINARY15TAP AC Switching Characteristics Over the Operating Range[9, 10]Parameter Description Min. Max UnittTCYCTCK Clock

CY7C1354V25CY7C1356V25PRELIMINARY16TAP Timing and Test Conditions(a)TDOCL=20 pFZ0=50ΩGND1.25VTest ClockTest Mode SelectTCKTMSTest Data-InTDITest Data

CY7C1354V25CY7C1356V25PRELIMINARY17Identification Register DefinitionsInstruction Field Value DescriptionRevision Number(31:28)TBD Reserved for versi

CY7C1354V25CY7C1356V25PRELIMINARY18Boundary Scan OrderBit #Signal NameBump IDBit #Signal NameBump ID1 TBD TBD 36 TBD TBD2 TBD TBD 37 TBD TBD3 TBD TBD

CY7C1354V25CY7C1356V25PRELIMINARY19Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperatur

CY7C1354V25CY7C1356V25PRELIMINARY2Pin ConfigurationsAAAAA1A0DNUDNUVSSVDDDNUAAAAAAVDDQVSSDQb DQb DQb VSSVDDQDQb DQb VSSVDD VDDDQaDQaVDDQVSSDQaDQaVSSVD

CY7C1354V25CY7C1356V25PRELIMINARY20Capacitance[15]Parameter Description Test Conditions Max. UnitCIN Input Capacitance TA = 25°C, f = 1 MHz,VDD = VD

CY7C1354V25CY7C1356V25PRELIMINARY21Switching Characteristics Over the Operating Range[16]-200 -166 -133 -100Parameter Description Min. Max. Min. Max.

CY7C1354V25CY7C1356V25PRELIMINARY22Switching Waveforms CENCLKADDRESSCEWE & Data-In/OuttCYCtCHtCLRA1tAHtAStWStWHtCEStCEHtCOQ4Q1= DON’T CARE= UNDEF

CY7C1354V25CY7C1356V25PRELIMINARY23Switching Waveforms (continued)ADV/LDCLKADDRESSCEData-In/OuttCYCtCHtCLtALStALHRA1tAHtAStCEStCEHtCOQ1= DON’T CARE=

CY7C1354V25CY7C1356V25PRELIMINARY24Document #: 38-00762-ASwitching Waveforms (continued)OEThree-StateI/OsOE TimingtEOHZtEOVtEOLZOrdering Information

CY7C1354V25CY7C1356V25PRELIMINARY25Package Diagram100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A10151-85050-A

CY7C1354V25CY7C1356V25PRELIMINARY© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cyp

CY7C1354V25CY7C1356V25PRELIMINARY3Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUDQaVDDQNCNCDQcDQdDQcDQdAA AA16M VDDQCE2AVDDQVDDQVDDQVDDQNC64M

CY7C1354V25CY7C1356V25PRELIMINARY4Pin Definitions (100-Pin TQFP)x18 Pin Location x36 Pin Location Name I/O Type Description37, 36, 32–35, 44–50, 80–8

CY7C1354V25CY7C1356V25PRELIMINARY574, 24 51, 80, 1, 30 DPaDPbDPcDPdI/O-SynchronousBidirectional Data Parity I/O lines. Functionally, these sig-nals a

CY7C1354V25CY7C1356V25PRELIMINARY6B6 B6 CE3Input-SynchronousChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction w

CY7C1354V25CY7C1356V25PRELIMINARY7U5 U5 TDO JTAG serial outputSynchronousSerial data-out to the JTAG circuit. Delivers data on the negative edge of T

CY7C1354V25CY7C1356V25PRELIMINARY8IntroductionFunctional OverviewThe CY7C1354V25/1356V25 are synchronous-pipelinedBurst NoBL SRAMs designed specifica

CY7C1354V25CY7C1356V25PRELIMINARY9Notes:1. X = ”don't care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 sign