CY7C1354V25
CY7C1356V25
PRELIMINARY
4
Pin Definitions (100-Pin TQFP)
x18 Pin Location x36 Pin Location Name I/O Type Description
37, 36, 32–35,
44–50, 80–83, 99,
100
37, 36, 32–35,
44–50, 81-83, 99,
100
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the 266,144 ad-
dress locations. Sampled at the rising edge of the CLK.
93, 94 93, 94, 95, 96 BWS
a
BWS
b
BWS
c
BWS
d
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE
to conduct writes to the SRAM. Sampled on the rising
edge of CLK. BWS
a
controls DQ
a
and DP
a
, BWS
b
con-
trols DQ
b
and DP
b
, BWS
c
controls DQ
c
and DP
c
, BWS
d
controls DQ
d
and DP
d
.
88 88 WE Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN
is active LOW. This signal must be
asserted LOW to initiate a write sequence.
85 85 ADV/LD Input-
Synchronous
Advance/Load Input used to advance the on-chip ad-
dress counter or load a new address. When HIGH (and
CEN
is asserted LOW) the internal burst counter is ad-
vanced. When LOW, a new address can be loaded into
the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
89 89 CLK Input-Clock Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN
. CLK is only rec-
ognized if CEN
is active LOW.
98 98 CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
2
and CE
3
to
select/deselect the device.
97 97 CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and CE
3
to
select/deselect the device.
92 92 CE
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and
CE
2
to
select/deselect the device.
86 86 OE Input-
Asynchronous
Output Enable, active LOW. Combined with the synchro-
nous logic block inside the device to control the direction
of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE
is masked
during the data portion of a write sequence, during the
first clock when emerging from a deselected state and
when the device has been deselected.
87 87 CEN Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW
the clock signal is recognized by the SRAM. When deas-
serted HIGH the clock signal is masked. Since deassert-
ing CEN
does not deselect the device, CEN can be used
to extend the previous cycle when required.
(a)58, 59, 62, 63,
68, 69, 72–74
(b)8, 9, 12, 13, 18,
19, 22–24
(a)52, 53, 56–59,
62, 63,
(b)68, 69, 72–75,
78, 79
(c)2, 3, 6–9, 12, 13,
(d)18, 19, 22–25,
28, 29
DQ
a
DQ
b
DQ
c
DQ
d
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[17:0]
during the previous
clock rise of the read cycle. The direction of the pins is
controlled by OE
and the internal control logic. When OE
is asserted LOW, the pins can behave as outputs. When
HIGH, DQ
a
–DQ
d
are placed in a three-state condition.
The outputs are automatically three-stated during the
data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE
.
(42 pages)
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