Cypress Semiconductor Perform CY7C1356C User Manual download pdf (Page 8)

CY7C1354V25

CY7C1356V25

PRELIMINARY

Introduction

Functional Overview

The CY7C1354V25/1356V25 are synchronous-pipelined

Burst NoBL SRAMs designed specifically to eliminate wait

states during Write/Read transitions. All synchronous inputs

pass through input registers controlled by the rising edge of

the clock. The clock signal is qualified with the Clock Enable

input signal (CEN

). If CEN is HIGH, the clock signal is not

recognized and all internal states are maintained. All synchro-

nous operations are qualified with CEN

. All data outputs pass

through output registers controlled by the rising edge of the

clock. Maximum access delay from the clock rise (t

) is 3.2

ns (200-MHz device).

Accesses can be initiated by asserting all three Chip Enables

(CE

, CE

) active at the rising edge of the clock. If Clock

Enable (CEN

) is active LOW and ADV/LD is asserted LOW, the

address presented to the device will be latched. The access

can either be a read or write operation, depending on the sta-

tus of the Write Enable (WE

). BWS

[d:a]

can be used to conduct

byte write operations.

Write operations are qualified by the Write Enable (WE

). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD

should be driven LOW once the device has been de-

selected in order to load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN

is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, (3) the Write Enable input

signal WE

is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory core

and control logic. The control logic determines that a read ac-

cess is in progress and allows the requested data to propagate

to the input of the output register. At the rising edge of the next

clock the requested data is allowed to propagate through the

output register and onto the data bus within 3.2 ns (200-MHz

device) provided OE

is active LOW. After the first clock of the

read access the output buffers are controlled by OE

and the

internal control logic. OE

must be driven LOW in order for the

device to drive out the requested data. During the second

clock, a subsequent operation (Read/Write/Deselect) can be

initiated. Deselecting the device is also pipelined. Therefore,

when the SRAM is deselected at clock rise by one of the chip

enable signals, its output will three-state following the next

clock rise.

Burst Read Accesses

The CY7C1354V25/1356V25 have an on-chip burst counter

that allows the user the ability to supply a single address and

conduct up to four Reads without reasserting the address in-

puts. ADV/LD

must be driven LOW in order to load a new ad-

dress into the SRAM, as described in the Single Read Access

section above. The sequence of the burst counter is deter-

mined by the MODE input signal. A LOW input on MODE se-

lects a linear burst mode, a HIGH selects an interleaved burst

sequence. Both burst counters use A0 and A1 in the burst

sequence, and will wrap-around when incremented sufficient-

ly. A HIGH input on ADV/LD

will increment the internal burst

counter regardless of the state of chip enables inputs or WE

is latched at the beginning of a burst cycle. Therefore, the

type of access (Read or Write) is maintained throughout the

burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN

is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, and (3) the write signal WE

is asserted LOW. The address presented to A

–A

is loaded

into the Address Register. The write signals are latched into

the Control Logic block.

On the subsequent clock rise the data lines are automatically

three-stated regardless of the state of the OE

input signal. This

allows the external logic to present the data on DQ

and DQP

(DQ

a,b,c,d

/DP

a,b

for CY7C1354V25 and DQ

a,b

/DP

a,b

for

CY7C1356V25). In addition, the address for the subsequent

access (Read/Write/Deselect) is latched into the Address

ed).

On the next clock rise the data presented to DQ

and DP

(DQ

a,b,c,d

/DP

a,b

for CY7C1354V25 & DQ

a,b

/DP

a,b

for

CY7C1356V25) (or a subset for byte write operations, see

Write Cycle Description table for details) inputs is latched into

the device and the write is complete.

The data written during the Write operation is controlled by

BWS

(BWS

a,b,c,d

for CY7C1354V25 & BWS

a,b

for

CY7C1356V25) signals. The CY7C1354V25/56V25 provides

byte write capability that is described in the Write Cycle De-

scription table. Asserting the Write Enable input (WE

) with the

selected Byte Write Select (BWS

) input will selectively write to

only the desired bytes. Bytes not selected during a byte write

operation will remain unaltered. A Synchronous self-timed

write mechanism has been provided to simplify the write oper-

ations. Byte write capability has been included in order to

greatly simplify Read/Modify/Write sequences, which can be

reduced to simple byte write operations.

Because the CY7C1354V25/56V25 is a common I/O device,

data should not be driven into the device while the outputs are

active. The Output Enable (OE

) can be deasserted HIGH be-

fore presenting data to the DQ

and DP (DQ

a,b,c,d

/DP

a,b

for

CY7C1354V25 & DQ

a,b

/DP

a,b

for CY7C1356V25) inputs. Do-

ing so will three-state the output drivers. As a safety precau-

tion, DQ

and DP (DQ

a,b,c,d

/DP

a,b

for CY7C1354V25 &

a,b

/DP

a,b

for CY7C1356V25) are automatically three-

stated during the data portion of a write cycle, regardless of

the state of OE

Burst Write Accesses

The CY7C1354V25/56V25 has an on-chip burst counter that

allows the user the ability to supply a single address and con-

duct up to four WRITE operations without reasserting the ad-

dress inputs. ADV/LD

must be driven LOW in order to load the

initial address, as described in the Single Write Access section

above. When ADV/LD

is driven HIGH on the subsequent clock

rise, the chip enables (CE

, CE

, and CE

) and WE inputs are

ignored and the burst counter is incremented. The correct

BWS

(BWS

a,b,c,d

for CY7C1354V25 & BWS

a,b

for

CY7C1356V25) inputs must be driven in each cycle of the

burst write in order to write the correct bytes of data.

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 25 26

Comments to this Manuals

No comments

Cypress Semiconductor Perform CY7C1356C User Manual Page 8

Comments to this Manuals

Related products and manuals for Unknown Cypress Semiconductor Perform CY7C1356C