Cypress Semiconductor Perform CY7C1356C User Manual download pdf (Page 11)

CY7C1354V25

CY7C1356V25

PRELIMINARY

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1354V25/56V25 incorporates a serial boundary

scan Test Access Port (TAP) in the BGA package only. The

TQFP package does not offer this functionality. This port oper-

ates in accordance with IEEE Standard 1149.1-1900, but does

not have the set of functions required for full 1149.1 compli-

ance. These functions from the IEEE specification are exclud-

ed because their inclusion places an added delay in the critical

speed path of the SRAM. Note that the TAP controller func-

tions in a manner that does not conflict with the operation of

other devices using 1149.1 fully compliant TAPs. The TAP op-

erates using JEDEC standard 2.5V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

) to prevent clocking of the device. TDI and TMS are in-

ternally pulled up and may be unconnected. They may alter-

nately be connected to V

through a pull-up resistor. TDO

should be left unconnected. Upon power-up, the device will

come up in a reset state which will not interfere with the oper-

ation of the device.

Test Access Port (TAP) - Test Clock

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the regis-

ters and can be connected to the input of any of the registers.

The register between TDI and TDO is chosen by the instruc-

tion that is loaded into the TAP instruction register. For infor-

mation on loading the instruction register, see the TAP Con-

troller State Diagram. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is

connected to the Most Significant Bit (MSB) on any register.

Test Data Out (TDO)

The TDO output pin is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine (see TAP Controller State Dia-

gram). The output changes on the falling edge of TCK. TDO is

connected to the Least Significant Bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (V

) for five rising

edges of TCK. This RESET does not affect the operation of the

SRAM and may be performed while the SRAM is operating. At

power-up, the TAP is reset internally to ensure that TDO

comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test circuit-

ry. Only one register can be selected at a time through the

instruction registers. Data is serially loaded into the TDI pin on

the rising edge of TCK. Data is output on the TDO pin on the

falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

TDI and TDO pins as shown in the TAP Controller Block Dia-

gram. Upon power-up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as de-

scribed in the previous section.

When the TAP controller is in the CaptureIR state, the two least

significant bits are loaded with a binary “01” pattern to allow for

fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain states. The bypass

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices. The x36 configuration has a xx-bit-long regis-

ter, and the x18 configuration has a yy-bit-long register.

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ring.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register Defi-

nitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit in-

struction register. All combinations are listed in the Instruction

Code table. Three of these instructions are listed as RE-

SERVED and should not be used. The other five instructions

are described in detail below.

The TAP controller used in this SRAM is not fully compliant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented. The TAP controller can-

not be used to load address, data, or control signals into the

SRAM and cannot preload the Input or Output buffers. The

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