CY7C1354V25
CY7C1356V25
PRELIMINARY
5
74, 24 51, 80, 1, 30 DP
a
DP
b
DP
c
DP
d
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these sig-
nals are identical to DQ
[31:0]
. During write sequences,
DP
a
is controlled by BWS
a
, DP
b
is controlled by BWS
b
,
DP
c
is controlled by BWS
c
, and DP
d
is controlled by
BWS
d
.
31 31 MODE Input
Strap Pin
Mode Input. Selects the burst order of the device. Tied
HIGH selects the interleaved burst order. Pulled LOW
selects the linear burst order. MODE should not change
states during operation. When left floating MODE will de-
fault HIGH, to an interleaved burst order.
14 14 SN Input-
Asynchronous
This is a reserved pin. Tie it to V
DD
for normal operation.
15, 16, 41, 65, 66,
91
15, 16, 41, 65, 66,
91
V
DD
Power Supply Power supply inputs to the core of the device.
4, 11, 20, 27, 54,
61, 70, 77
4, 11, 20, 27, 54,
61, 70, 77
V
DDQ
I/O Power
Supply
Power supply for the I/O circuitry.
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
V
SS
Ground Ground for the device. Should be connected to ground of
the system.
NC - No connects. Reserved for address expansion to 512K
depths.
38, 39, 42, 43 38, 39, 42, 43 DNU - Do Not Use pins. These pins should be left floating.
Pin Definitions (100-Pin TQFP)
(continued)
x18 Pin Location x36 Pin Location Name I/O Type Description
Pin Definitions (119 BGA)
x18 Pin Location x36 Pin Location Name I/O Type Description
P4, N4, A2, A3, A5,
A6, B3, B5, C2, C3,
C5, C6, G4, R2, R6,
T2, T3, T5, T6
P4, N4, A2, A3, A5,
A6, B3, B5, C2, C3,
C5, C6, R2, R6, G4,
T3, T4, T5
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the 266,144
address locations. Sampled at the rising edge of the
CLK.
L5, G3 L5, G5, G3, L3 BWS
a
BWS
b
BWS
c
BWS
d
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with
WE
to conduct writes to the SRAM. Sampled on the
rising edge of CLK. BWS
a
controls DQ
a
and DP
a
,
BWS
b
controls DQ
b
and DP
b
, BWS
c
controls DQ
c
and DP
c
, BWS
d
controls DQ
d
and DP
d
.
H4 H4 WE Input-
Synchronous
Write Enable Input, active LOW. Sampled on the ris-
ing edge of CLK if CEN
is active LOW. This signal
must be asserted LOW to initiate a write sequence.
B4 B4 ADV/LD Input-
Synchronous
Advance/Load Input used to advance the on-chip ad-
dress counter or load a new address. When HIGH
(and CEN
is asserted LOW) the internal burst
counter is advanced. When LOW, a new address can
be loaded into the device for an access. After being
deselected, ADV/LD
should be driven LOW in order
to load a new address.
K4 K4 CLK Input-Clock Clock Input. Used to capture all synchronous inputs
to the device. CLK is qualified with CEN
. CLK is only
recognized if CEN
is active LOW.
E4 E4 CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
2
and
CE
3
to select/deselect the device.
B2 B2 CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and
CE
3
to select/deselect the device.
(42 pages)
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