Cypress Semiconductor Perform CY7C1356C User Manual download pdf (Page 7)

CY7C1354V25

CY7C1356V25

PRELIMINARY

U5 U5 TDO JTAG serial

output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on

the negative edge of TCK.

U3 U3 TDI JTAG serial

input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the

rising edge of TCK.

U2 U2 TMS Test Mode Se-

lect

Synchronous

This pin controls the Test Access Port state machine.

Sampled on the rising edge of TCK.

U4 U4 TCK JTAG-Clock Clock input to the JTAG circuitry.

A4, T6, T2 A4, T4, T1 16M,

32M,

64M

- No connects. Reserved for address expansion.

B1, B7, C1, C7, D2,

D4, D7, E1, E6, F2,

G1, G5, G6, H2,

H7, K1, K6, L2, L3,

L4, M6, N2, N7, P1,

P6, R1, R7

B7, C7, D4, L4, R1,

R7, T1

NC - No connects.

U6 U6 DNU - Do not use pins.

Pin Definitions (119 BGA)

(continued)

x18 Pin Location x36 Pin Location Name I/O Type Description

1 2 3 4 5 6 7 8 9 10 11 12 ... 25 26

No comments

Cypress Semiconductor Perform CY7C1356C User Manual Page 7