Cypress Semiconductor Perform CY7C1356C User Manual download pdf (Page 6)

CY7C1354V25

CY7C1356V25

PRELIMINARY

B6 B6 CE

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the

rising edge of CLK. Used in conjunction with CE

and

to select/deselect the device.

F4 F4 OE Input-

Asynchronous

Output Enable, active LOW. Combined with the syn-

chronous logic block inside the device to control the

direction of the I/O pins. When LOW, the I/O pins are

allowed to behave as outputs. When deasserted

HIGH, I/O pins are three-stated, and act as input data

pins. OE

is masked during the data portion of a write

sequence , during the first clock when emerging from

a deselected state and when the device has been

deselected.

M4 M4 CEN Input-

Synchronous

Clock Enable Input, active LOW. When asserted

LOW the clock signal is recognized by the SRAM.

When deasserted HIGH the clock signal is masked.

Since deasserting CEN

does not deselect the device,

CEN

can be used to extend the previous cycle when

required.

(a)P7, N6, L6, K7,

H6, G7, F6, E7

(b)N1, M2, L1, K2,

H1, G2, E2, D1

(a)P7, N7, N6, M6,

L7, L6, K7, K6

(b)D7, E7, E6, F6,

G7, G6, H7, H6

(c)D1, E1, E2, F2,

G1, G2, H1, H2

(d)P1, N1, N2, M2,

L1, L2, K1, K2

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into

an on-chip data register that is triggered by the rising

edge of CLK. As outputs, they deliver the data con-

tained in the memory location specified by A

[17:0]

dur-

ing the previous clock rise of the read cycle. The di-

rection of the pins is controlled by OE

and the internal

control logic. When OE

is asserted LOW, the pins can

behave as outputs. When HIGH, DQ

–DQ

are

placed in a three-state condition. The outputs are au-

tomatically three-stated during the data portion of a

write sequence, during the first clock when emerging

from a deselected state, and when the device is de-

selected, regardless of the state of OE

D6, P2 P6, D6, D2, P2 DP

I/O-

Synchronous

Bidirectional Data Parity I/O lines. Functionally, these

signals are identical to DQ

[31:0]

. During write se-

quences, DP

is controlled by BWS

, DP

is con-

trolled by BWS

, DP

is controlled by BWS

, and DP

is controlled by BWS

R3 R3 MODE Input

Strap pin

Mode Input. Selects the burst order of the device.

Tied HIGH selects the interleaved burst order. Pulled

LOW selects the linear burst order. MODE should not

change states during operation. When left floating

MODE will default HIGH, to an interleaved burst

order.

C4, J2, J4, J6, R4 C4, J2, J4, J6, R4 V

Power Supply Power supply inputs to the core of the device.

A1, A7, F1, F7, J1,

J7, M1, M7, U1, U7

A1, A7, F1, F7, J1,

J7, M1, M7, U1, U7

DDQ

I/O Power

Supply

Power supply for the I/O circuitry.

D3, D5, E3, E5, F3,

F5, H3, H5, K3, K5,

M3, M5, N3, N5,

P3, P5, R5

D3, D5, E3, E5, F3,

F5, H3, H5, K3, K5,

M3, M5, N3, N5, P3,

P5, R5

Ground Ground for the device. Should be connected to

ground of the system.

T7 T7 ZZ -

R5 R5 SN Input-

Asynchronous

This is a reserved pin. Tie it to V

for normal oper-

ation.

J3, J5 J3, J5 V

dd(1)

Input-

Asynchronous

These pins have to be tied to a voltage level > Vih.

They need not be tied to Vdd.

Pin Definitions (119 BGA)

(continued)

x18 Pin Location x36 Pin Location Name I/O Type Description

1 2 3 4 5 6 7 8 9 10 11 ... 25 26

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