Cypress Semiconductor ISR 37000 CPLD User Manual

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Ultra37000 CPLD Family
5V and 3.3V ISR™ High Performance
CPLDs
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number : 38-03007 Rev. *G Revised March 19, 2010
Features
In-System Reprogrammable™ (ISR™) CMOS CPLDs
JTAG interface for reconfigurability
Design changes do not cause pinout changes
Design changes do not cause timing changes
High Density
32 to 512 macrocells
32 to 264 I/O pins
5 dedicated inputs including 4 clock pins
Simple Timing Model
No fanout delays
No expander delays
No dedicated vs. I/O pin delays
No additional delay through PIM
No penalty for using full 16 product terms
No delay for steering or sharing product terms
3.3V and 5V Versions
PCI Compatible
[1]
Programmable Bus-hold Capabilities on All I/Os
Intelligent Product Term Allocator Provides
0 to 16 product terms to any macrocell
Product term steering on an individual basis
Product term sharing among local macrocells
Flexible Clocking
4 synchronous clocks per device
Product term clocking
Clock polarity control per logic block
Consistent Package and Pinout Offering across All
Densities
Simplifies design migration
Same pinout for 3.3V and 5V devices
Packages
44 to 256 Pins in PLCC, PQFP, TQFP, and Fine-Pitch BGA
Packages
Pb-free packages available
General Description
The Ultra37000™ family of CMOS CPLDs provides a range of
high density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to bring
the flexibility, ease of use, and performance of the 22V10 to high
density CPLDs. The architecture is based on a number of logic
blocks that are connected by a Programmable Interconnect
Matrix (PIM). Each logic block features its own product term
array, product term allocator, and 16 macrocells. The PIM
distributes signals from the logic block outputs and all input pins
to the logic block inputs.
All the Ultra37000 devices are electrically erasable and
In-System Reprogrammable (ISR), which simplifies both design
and manufacturing flows, thereby reducing costs. The ISR
feature provides the ability to reconfigure the devices without
having design changes cause pinout or timing changes. The
Cypress ISR function is implemented through a JTAG-compliant
serial interface. Data is shifted in and out through the TDI and
TDO pins, respectively. Because of the superior routability and
simple timing model of the Ultra37000 devices, ISR allows users
to change existing logic designs while simultaneously fixing
pinout assignments and maintaining system performance.
The entire family features JTAG for ISR and boundary scan, and
is compatible with the PCI Local Bus specification, meeting the
electrical and timing requirements. The Ultra37000 family
features user programmable bus-hold capabilities on all I/Os.
Ultra37000 5V Devices
The Ultra37000 devices operate with a 5V supply and can
support 5V or 3.3V I/O levels. V
CCO
connections provide the
capability of interfacing to either a 5V or 3.3V bus. By connecting
the V
CCO
pins to 5V the user insures 5V TTL levels on the
outputs. If V
CCO
is connected to 3.3V the output levels meet 3.3V
JEDEC standard CMOS levels and are 5V tolerant. These
devices require 5V ISR programming.
Ultra37000V 3.3V Devices
Devices operating with a 3.3V supply require 3.3V on all V
CCO
pins, reducing the device’s power consumption. These devices
support 3.3V JEDEC standard CMOS output levels, and are
5V-tolerant. These devices allow 3.3V ISR programming.
Note
1. Due to the 5V tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V
CC
, PCI V
IH
= 2V.
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Summary of Contents

Page 1 - Ultra37000 CPLD Family

Ultra37000 CPLD Family5V and 3.3V ISR™ High PerformanceCPLDsCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-94

Page 2

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 10 of 43Logic Block DiagramsCY37032/CY37032VLOGICBLOCKBLOGICBLOCKA36163616InputClock/

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 11 of 43Logic Block Diagrams (continued)TDITCKTMSTDOJTAG TapControllerCY37128/CY37128

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 12 of 43Logic Block Diagrams (continued)CY37256/CY37256V LOGICBLOCKGLOGICBLOCKHLOGICB

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 13 of 435V Device Maximum RatingsExceeding maximum ratings may shorten the useful lif

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 14 of 433.3V Device Maximum RatingsExceeding maximum ratings may shorten the useful l

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 15 of 43 Inductance[5]Parameter Description Test Conditions44- Pin TQFP44- Pin PLCC10

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 16 of 43Parameter[11]VXOutput Waveform—Measurement LeveltER(–)1.5VtER(+)2.6VtEA(+)1.5

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 17 of 43Product Term Clocking ParameterstCOPT[13, 14, 15]Product Term Clock or Latch

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 18 of 43Switching Characteristics Over the Operating Range[12]Parameter200 MHz 167 MH

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 19 of 43tRO[13, 14, 15]12 13 13 14 15 18 21 26 nstPW8 8 8 8 10 12 15 20 nstPR[13]10 1

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 2 of 43ContentsFeatures ...

Page 13

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 20 of 43Figure 11. Registered Output with Product Term Clocking Input Going Through

Page 14

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 21 of 43Figure 14. Registered InputFigure 15. Clock to ClockFigure 16. Latched Inp

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 22 of 43Figure 17. Latched Input and OutputFigure 18. Asynchronous ResetSwitching W

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 23 of 43Power ConsumptionFigure 19. Asynchronous PresetFigure 20. Output Enable/Dis

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 24 of 43CY37064CY37128Typical 5V Power Consumption (continued)The typical pattern is

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 25 of 43CY37192CY37256Typical 5V Power Consumption (continued)0501001502002503000 20

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 26 of 43Typical 3.3V Power ConsumptionCY37032VCY37064V0510152025300 20 40 60 80 100 1

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 27 of 43CY37128VCY37192VTypical 3.3V Power Consumption (continued)010203040506070800

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 28 of 43CY37256VTypical 3.3V Power Consumption (continued)0204060801001201400 20 40 6

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 29 of 43Pin Configurations[20]Notes20.For 3.3V versions (Ultra37000V), VCCO = VCC.21.

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 3 of 43Selection Guide5V Selection Guide Table 1. General InformationDevice Macroce

Page 24

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 30 of 43Pin Configurations[20] (continued)Top View100-Pin TQFP (A100)100 9798 9623142

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 31 of 43Pin Configurations[20] (continued)I/O7712412312212112011911811711611511411311

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 32 of 43Pin Configurations[20] (continued)I/O7212412312212112011911811711611511411311

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 33 of 43Pin Configurations[20] (continued)256-Ball Fine-Pitch BGA (BB256)Top View1 2

Page 28

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 34 of 43Ordering Information5V Ordering InformationMacrocells Speed(MHz)Ordering Code

Page 29

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 35 of 43Addendum3.3V Operating RangeCY37064VP100-143AXC, CY37064VP44-143AXC256 125 CY

Page 30

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 36 of 43Package DiagramsFigure 21. 44-Pin Pb-free Thin Plastic Quad Flat Pack A44Fig

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 37 of 43Figure 23. 100-Pin Pb-free Thin Plastic Quad Flat Pack (TQFP) A10051-85048 *

Page 32

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 38 of 43Figure 24. 160-Pin Pb-free Thin Plastic Quad Flat Pack (24 x 24 x 1.4 mm) (T

Page 33

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 39 of 43Figure 25. 256-Ball FBGA (17 x 17 mm) BB25651-85108 *H[+] Feedback

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 4 of 43Architecture Overview of Ultra37000 FamilyProgrammable Interconnect MatrixThe

Page 35

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 40 of 43Document History PageDocument Title: Ultra37000 CPLD Family 5V and 3.3V ISR™

Page 36

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 41 of 43*F 2813051 12/04/09 AAE a.In the features section, reduced the maximum number

Page 37

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 42 of 43CY37256P160-83AI, CY37256P208-83NI, CY37256P256-83BGI, CY37384P208-125NC, CY3

Page 38

Document Number : 38-03007 Rev. *G Revised March 19, 2010 Page 43 of 43ViewDraw and SpeedWave are trademarks of ViewLogic. Windows is a registered t

Page 39

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 5 of 43Low Power OptionEach logic block can operate in high speed mode for critical p

Page 40

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 6 of 43Figure 2. I/O and Buried MacrocellsFigure 3. Input MacrocellC2 C3DECODEC2 C3

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 7 of 43Figure 4. Input/Clock MacrocellClockingEach I/O and buried macrocell has acce

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Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 8 of 43JTAG and PCI StandardsPCI Compliance5V operation of the Ultra37000 is fully co

Page 43

Ultra37000 CPLD FamilyDocument Number : 38-03007 Rev. *G Page 9 of 43The second method for programming Ultra37000 devices is onautomatic test equip

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