Cypress Semiconductor ISR 37000 CPLD User Manual Page 23

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Ultra37000 CPLD Family
Document Number : 38-03007 Rev. *G Page 23 of 43
Power Consumption
Figure 19. Asynchronous Preset
Figure 20. Output Enable/Disable
Switching Waveforms (continued)
INPUT
t
PO
REGISTERED
OUTPUT
CLOCK
t
PR
t
PW
INPUT
t
ER
OUTPUTS
t
EA
Typical 5V Power Consumption
CY37032
0
10
20
30
40
50
60
0 50 100 150 200 250
Frequency (MHz)
Icc (mA)
High Speed
Low Power
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 5V, T
A
= Room Temperature
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