Cypress Semiconductor ISR 37000 CPLD User Manual Page 16

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Ultra37000 CPLD Family
Document Number : 38-03007 Rev. *G Page 16 of 43
Parameter
[11]
V
X
Output Waveform—Measurement Level
t
ER(–)
1.5V
t
ER(+)
2.6V
t
EA(+)
1.5V
t
EA(–)
V
the
(d) Test Waveforms
V
OH
V
X
0.5V
V
OL
V
X
0.5V
V
X
V
OH
0.5V
V
X
V
OL
0.5V
Switching Characteristics Over the Operating Range
[12]
Parameter Description Unit
Combinatorial Mode Parameters
t
PD
[13, 14, 15]
Input to Combinatorial Output ns
t
PDL
[13, 14, 15]
Input to Output Through Transparent Input or Output Latch ns
t
PDLL
[13, 14, 15]
Input to Output Through Transparent Input and Output Latches ns
t
EA
[13, 14, 15]
Input to Output Enable ns
t
ER
[11, 13]
Input to Output Disable ns
Input Register Parameters
t
WL
Clock or Latch Enable Input LOW Time
[8]
ns
t
WH
Clock or Latch Enable Input HIGH Time
[8]
ns
t
IS
Input Register or Latch Set-up Time ns
t
IH
Input Register or Latch Hold Time ns
t
ICO
[13, 14, 15]
Input Register Clock or Latch Enable to Combinatorial Output ns
t
ICOL
[13, 14, 15]
Input Register Clock or Latch Enable to Output Through Transparent Output Latch ns
Synchronous Clocking Parameters
t
CO
[14, 15]
Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output ns
t
S
[13]
Set-Up Time from Input to Sync. Clk (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable ns
t
H
Register or Latch Data Hold Time ns
t
CO2
[13, 14, 15]
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Combinatorial Output
Delay (Through Logic Array)
ns
t
SCS
[13]
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output Synchronous
Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable (Through Logic Array)
ns
t
SL
[13]
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK
0
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
ns
t
HL
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK
0
,
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
ns
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