Cypress Semiconductor Perform CY7C1356C User Manual download pdf (Page 23)

CY7C1354V25

CY7C1356V25

PRELIMINARY

Switching Waveforms

(continued)

ADV/LD

CLK

ADDRESS

Data-

In/Out

CYC

ALS

ALH

RA1

CES

CEH

= DON’T CARE

= UNDEFINED

The combination of WE & BWS

(x = a, b c, d) define a write cycle (see Write Cycle Description table).

Out

Begin Read

Burst Read

CLZ

DOH

CE is the combination of CE

, CE

, and CE

. All chip enables need to be active in order to select

the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for

Device

originally

deselected

Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN

held

WA2

Q1+1

Out

Q1+2

Out

Q1+3

Out

RA3

CLZ

CHZ

D2+1

D2+2

D2+3

Out

Burst Read

Begin Write

Burst Write

Begin Read

Burst Read

Burst Sequences

BWS

LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS

input signals.

Burst order determined by the state of the MODE input. CEN

held LOW. OE held LOW.

1 2 ... 18 19 20 21 22 23 24 25 26

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Cypress Semiconductor Perform CY7C1356C User Manual Page 23

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