Cypress Semiconductor Perform CY7C1356C User Manual download pdf (Page 17)

CY7C1354V25

CY7C1356V25

PRELIMINARY

Identification Register Definitions

Instruction Field Value Description

Revision Number

(31:28)

TBD Reserved for version number.

Device Depth

(27:23)

TBD Defines depth of SRAM.

Device Width

(22:18)

TBD Defines with of the SRAM.

Cypress Device ID

(17:12)

TBD Reserved for future use.

Cypress JEDEC ID

(11:1)

TBD Allows unique identification of SRAM vendor.

ID Register Presence

(0)

TBD Indicate the presence of an ID register.

Scan Register sizes

Instruction 3

Bypass 1

ID 32

Boundary Scan TBD

Identification Codes

Instruction Code Description

EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register

between the TDI and TDO. Forces all SRAM outputs to High-Z state. This

instruction is not 1149.1 compliant.

IDCODE 001 Loads the ID register with the vendor ID code and places the register be-

tween TDI and TDO. This operation does not affect SRAM operation.

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register be-

tween TDI and TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register

between TDI and TDO. Does not affect the SRAM operation. This instruction

does not implement 1149.1 preload function and is therefore not 1149.1

compliant.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not

affect SRAM operation.

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 25 26

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