Cypress Semiconductor Perform CY7C1356C User Manual download pdf (Page 9)

CY7C1354V25

CY7C1356V25

PRELIMINARY

Notes:

1. X = ”don't care,” 1 = Logic HIGH, 0 = Logic LOW, CE

stands for ALL Chip Enables active. BWS

= 0 signifies at least one Byte Write Select is active, BWS

Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE

and BWS

. See Write Cycle Description table for details.

3. The DQ and DP pins are controlled by the current cycle and the OE

signal.

4. CEN = 1 inserts wait states.

5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE

6. OE assumed LOW.

Cycle Description Truth Table

[1, 2, 3, 4, 5, 6]

Operation

Address

Used CE CEN

ADV/

LD/ WE BWS

CLK Comments

Deselected External 1 0 L X X L-H I/Os three-state following next

recognized clock.

Suspend - X 1 X X X L-H Clock ignored, all operations

suspended.

Begin Read External 0 0 0 1 X L-H Address latched.

Begin Write External 0 0 0 0 Valid L-H Address latched, data presented

two valid clocks later.

Burst Read

Operation

Internal X 0 1 X X L-H Burst Read operation. Previous ac-

cess was a Read operation. Ad-

dresses incremented internally in

conjunction with the state of Mode.

Burst Write

Operation

Internal X 0 1 X Valid L-H Burst Write operation. Previous ac-

cess was a Write operation. Ad-

dresses incremented internally in

conjunction with the state of

MODE. Bytes written are deter-

mined by BWS

[d:a]

Interleaved Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

A[1:0] A[1:0] A[1:0] A[1:0]

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

A[1:0] A[1:0] A[1:0] A[1:0]

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 25 26

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