Cypress Semiconductor Perform CY8C24x94 Specifications download pdf (Page 43)

CY8C24123A

CY8C24223A

CY8C24423A

Document Number: 38-12028 Rev. *V Page 43 of 71

When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up

to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 K resistance and the external capacitor.

Figure 14. Typical AGND Noise with P2[4] Bypass

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry.

At high frequencies, increased power level reduces the noise spectrum level.

Table 35. 2.7-V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units

ROA

Rising settling time from 80% of V to 0.1% of V

(10 pF load, unity gain)

Power = low, Opamp bias = low

Power = medium, Opamp bias = high

–

3.92

0.72

µs

SOA

Falling settling time from 20% of V to 0.1% of V

(10 pF load, unity gain)

Power = low, Opamp bias = low

Power = medium, Opamp bias = high

–

5.41

0.72

µs

ROA

Rising slew rate (20% to 80%) (10 pF load, unity gain)

Power = low, Opamp bias = low

Power = medium, Opamp bias = high

0.31

2.7

–

V/µs

FOA

Falling slew rate (20% to 80%) (10 pF load, unity gain)

Power = low, Opamp bias = low

Power = medium, Opamp bias = high

0.24

1.8

–

V/µs

Gain bandwidth product

Power = low, Opamp bias = low

Power = medium, Opamp bias = high

0.67

2.8

–

MHz

NOA

Noise at 1 kHz (Power = medium, Opamp bias = high) – 100 – nV/rt-Hz



100

1000

10000

0.001 0.01 0.1 1 10 100Fr eq (kHz)

nV/rtHz

0.01

0.1

1.0

1 2 ... 38 39 40 41 42 43 44 45 46 47 48 ... 70 71

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Cypress Semiconductor Perform CY8C24x94 Specifications Page 43

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