Cypress Semiconductor Perform CY8C24x94 Specifications download pdf (Page 40)

CY8C24123A

CY8C24223A

CY8C24423A

Document Number: 38-12028 Rev. *V Page 40 of 71

Figure 11. PLL Lock Timing Diagram

Figure 12. PLL Lock for Low Gain Setting Timing Diagram

Figure 13. External Crystal Oscillator Startup Timing Diagram

24 MHz

F

PLL

PLL

Enable

T

PLLSLEW

PLL

Gain

0

24 MHz

F

PLL

PLL

Enable

T

PLLSLEWLOW

PLL

Gain

1

32 kHz

F

32K2

32K

Select

T

OS

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 70 71

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