Cypress Semiconductor Perform CY8C24x94 Specifications download pdf (Page 38)

CY8C24123A

CY8C24223A

CY8C24423A

Document Number: 38-12028 Rev. *V Page 38 of 71

DC24M 24 MHz duty cycle 40 50 60 %

ILO

ILO duty cycle 20 50 80 %

Step24M 24 MHz trim step size – 50 – kHz

Fout48M 48 MHz output frequency 46.8 48.0 49.2

[24, 25]

MHz Trimmed. Using factory trim values.

MAX

Maximum frequency of signal on row input

or row output.

– – 12.3 MHz

POWER_UP

Power supply slew rate – – 250 V/ms V

slew rate during power-up.

POWERUP

Time from end of POR to CPU executing

code

– 16 100 ms Power-up from 0 V. See the System

Resets section of the PSoC

Technical Reference Manual.

jit_IMO

[26]

24 MHz IMO cycle-to-cycle jitter (RMS) – 200 700 ps N = 32

24 MHz IMO long term N cycle-to-cycle

jitter (RMS)

– 300 900 ps

24 MHz IMO period jitter (RMS) – 100 400 ps

jit_PLL

[26]

24 MHz IMO cycle-to-cycle jitter (RMS) – 200 800 ps N = 32

24 MHz IMO long term N cycle-to-cycle

jitter (RMS)

– 300 1200

24 MHz IMO period jitter (RMS) – 100 700

Table 29. 5-V and 3.3-V AC Chip-Level Specifications (continued)

Symbol Description Min Typ Max Units Notes

Notes

24. 4.75 V < V

< 5.25 V.

25. 3.0 V < V

< 3.6 V. See application note Adjusting PSoC

Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V.

26. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.

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