Cypress Semiconductor Perform CY8C24x94 User Manual Page 7

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PSoC® 1 ISSP Programming Specifications, Document No. 001-15239 Rev. *J 7
2. Host Programmer - PSoC
®
1 Programming Interface
Figure 2-1 shows the connections between the host programmer and the target PSoC
®
1 device. If you use a Miniprog1 pro-
grammer, refer to the knowledge base article at http://www.cypress.com/?id=4&rID=50010 for information about the part num-
ber of the Miniprog1 programming header.
Figure 2-1. Host Programmer - PSoC 1 Interface
2.1 Programming Pin Drive Modes
The electrical pin connections between the programmer and the target shown in Figure 2-1 are listed in Table 2-1. This
includes two signal pins, a reset pin, a power pin, and a ground pin. Leave the other pins floating. The pin-naming conven-
tions and drive-strength requirements are also listed in Table 2-1.
Table 2-1. Pin Names and Drive Strengths
Pin Name Function Programmer HW Pin Requirements PSoC 1 Drive mode behavior
P1[0] SDATA - Serial Data In/Out Drive TTL Levels, Read TTL, High Z Strong drive (while sending data to host),
Resistive pull down mode (Reading data
from host, Waiting for data from host)
P1[1] SCLK - Serial Clock Drive TTL Levels High Z Digital input
XRES Reset Drive TTL Levels. Active High Active high Reset input with internal resistive
pull down
V
SS
Power Supply Ground Connection Low Resistance Ground Connection Ground connection
V
DD
Positive Power Supply Voltage 0 V, 1.8 V, 3.3 V, 5 V. 20 mA Current Capability Supply voltage
V
SS
V
DD
*
SCLK(P1[1])
SDATA(P1[0])
XRES **
GND
GND
SCLK
SDATA
XRES
Host Programmer PSoC 1
V
DD
* For Programming in Power Cycle mode, the Host Programmer must be able to toggle power to the PSoC 1 device.
** XRES pin in PSoC 1 is an active-high input. It has an internal pull-down resistor to keep it at logic low when left
floating. XRES pin is not available in all device packages. Check the device datasheet for information on XRES pin
availability. Use Power Cycle mode if XRES is not available.
V
DD
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