Cypress Semiconductor Perform CY8C24x94 User Manual download pdf (Page 19)

PSoC® 1 ISSP Programming Specifications, Document No. 001-15239 Rev. *J 19

4. Specifications and Definitions

4.1 DC Programming Specifications

4.2 AC Programming Specifications

Table 4-1. DC Programming Specifications

DC Programming Specifications Minimum Maximum

DDp

(Supply Current During Programming or Verify)

See the DC Programming Specifications section in the respective

device datasheet

ilp

(Input Low Voltage During Programming or Verify)

ihp

(Input High Voltage During Programming or Verify)

ilp

(Input Current when Applying V

ilp

to P1[0] or P1[1] During Programming or Verify)

ihp

(Input Current when Applying V

ihp

to P1[0] or P1[1] During Programming or Verify)

olv

(Output Low Voltage During Programming or Verify IOL = 0.1 mA)

ohv

(Output High Voltage During Programming or Verify IOH = 5 mA)

ddp

for Programming and Erase)

for Verify)

ipor

(Power On Reset Trip)

See the DC POR and LVD Specifications section in the respective

device datasheet

Table 4-2. AC Programming Specifications

AC Programming Specifications Minimum Maximum

rsclk

(Rise Time of SCLK)

See the AC Programming Specifications

section in the respective device datasheet

fsclk

(Fall Time of SCLK)

ssclk

(Data Setup Time to Falling Edge of SCLK)

hsclk

(Data Hold Time From Falling Edge of SCLK)

sclk

(Frequency of SCLK)

dsclk

(Data-Out Delay from Falling Edge of SCLK)

vddwait

Stable to WAIT-AND-POLL Hold Off

[1]

)

0.1 ms 1 ms

poll

(SDATA High Pulse Time

[2]

)

10 µs 100 ms

acq

(Delay from WAIT-AND-POLL to Initialize-1

[3]

)

–3 ms

xres

(Duration of External Reset)

See the AC Chip Level Specifications in the

respective device datasheet

xresini

(Programming Mode Acquisition Window)

–125 µs

Notes

1. Until V

stabilizes, SDATA is noisy and the falling edge must not be pursued. Therefore, a delay of T

vddwait

is needed after V

is applied and before WAIT-

AND-POLL.

2. This applies to the WAIT-AND-POLL mnemonic. The SDATA remains high for T

poll

time.

3. The Initialize-1 bit-stream data must not be delayed more than T

acq

from the end of the WAIT-AND-POLL (measured from SDATA’s falling edge).

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