Cypress Semiconductor Perform CY8C24x94 User Manual Page 12

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12 PSoC® 1 ISSP Programming Specifications, Document No. 001-15239 Rev. *J
Programming Flow
3.2.2 Power Cycle Mode
To initiate communication with the target using power cycle mode, apply V
DD
to the target as shown in Figure 3-6. The target
attempts to drive the SDATA line high. The programmer then waits and polls for a high-to-low transition on the SDATA line,
which is the signal from the target that V
DD
has stabilized. Note that until V
DD
stabilizes, the SDATA signal is noisy and a false
edge could be detected. As a result, the programmer must wait for the time specified by T
VDDwait
(Table 4-2 on page 19)
before beginning to wait and poll. The programmer also must not drive the SCLK signal until the T
VDDwait
time period has
passed.
After the SDATA transition is detected, the programmer must transmit the Initialize 1 vectors in T
acq
seconds (see Table 4-2 on
page 19).
Next, send Initialize 2 vectors and wait for a high-to-low transition on SDATA. Send the appropriate Initialize 3 vectors for the
V
DD
level applied to the PSoC when it is programmed.
During the power cycle phase of the Initialize Target Procedure, V
DD
must be the only pin asserted. XRES must be low. The
PSoC’s internal pull-down resistor achieves this if the pin is left floating externally.
Figure 3-6. Using Power Cycling to Initialize
3.2.3 Verify Silicon ID Procedure
The Verify Silicon ID Procedure (see Figure 3-7 on page 12)
returns the package-specific silicon ID value from the target.
This is used by the programmer to verify the package type of
the target.
Figure 3-7. Verify Silicon ID Procedure
1
TVDD wait
V
DD
SDATA
SCLK
T
acq
1
Tssclk
TrsclkTfsclk
1
Fsclk
V
DD
= V
POR
Begin Verify Silicon
ID
Send ID Setup
Vectors
Wait and Poll for
SDATA going low
Read Back Silicon
ID Word
Correct Value?
End Verify Silicon
ID
Programming Failed
Yes
No
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