Cypress Semiconductor Perform CY8C24x94 Specifications Page 1

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CY8C21123/CY8C21223/CY8C21323
PSoC
®
Programmable System-on-Chip™
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-12022 Rev. *Y Revised August 20, 2014
PSoC
®
Programmable System-on-Chip
Features
Powerful Harvard-architecture processor:
M8C processor speeds up to 24 MHz
Low power at high speed
Operating voltage: 2.4 V to 5.25 V
Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
Industrial temperature range: –40 °C to +85 °C
Advanced peripherals (PSoC
®
blocks):
Four analog type “E” PSoC blocks provide:
Two comparators with digital to analog converter (DAC)
references
Single or dual 10-Bit 8-to-1 analog to digital converter
(ADC)
Four digital PSoC blocks provide:
8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
CRC and PRS modules
Full duplex UART, SPI master or slave: Connectable to all
general-purpose I/O (GPIO) pins
Complex peripherals by combining blocks
Flexible on-chip memory:
4 KB flash program storage 50,000 erase/write cycles
256 bytes SRAM data storage
In-system serial programming (ISSP)
Partial flash updates
Flexible protection modes
EEPROM emulation in flash
Complete development tools:
Free development software (PSoC Designer™)
Full-featured, in-circuit emulator (ICE) and programmer
Full-speed emulation
Complex breakpoint structure
128-KB trace memory
Precision, programmable clocking:
Internal ±5% 24- / 48-MHz main oscillator
Internal low-speed, low-power oscillator for watchdog and
sleep functionality
Programmable pin configurations:
25-mA sink, 10-mA source on all GPIOs
Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
Up to eight analog inputs on all GPIOs
Configurable interrupt on all GPIOs
Additional system resources:
I
2
C master, slave and multi-master to 400 kHz
Watchdog and sleep timers
User-configurable low-voltage detection (LVD)
Integrated supervisory circuit
On-chip precision voltage reference
Logic Block Diagram
DIGITAL SYSTEM
SRAM
System Bus
Interrupt
Controller
Sleep and
Watchdog
Clock Source s
(Includes IMO and ILO)
Global Digital Interconnect
Global Analog Interconnect
PSoC
CORE
CPU Core
(M8C)
SROM Flash
I2C
Internal
Voltage
Ref .
Digital
Cloc ks
POR and LVD
System Resets
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref .
Por t 1 Por t 0
Digital
PSoC Block
Array
Analog
PSoC Block
Array
Sw itch
Mode
Pump
Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above 70 °C),
frequency tolerance deviates from ±2.5% to ±5%. For information on silicon errata, see “Errata” on page 42.
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Summary of Contents

Page 1 - Programmable System-on-Chip™

CY8C21123/CY8C21223/CY8C21323PSoC® Programmable System-on-Chip™Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-

Page 2

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 10 of 4620-Pin Part Pinout Table 5. Pin Definitions – CY8C21323 20-Pin SSOPPin

Page 3

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 11 of 4624-Pin Part Pinout Table 6. Pin Definitions – CY8C21323 24-Pin QFN[5] Pi

Page 4

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 12 of 46Register ReferenceThis section lists the registers of the CY8C21x23 PSoC

Page 5

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 13 of 46Table 8. Register Map Bank 0 Table: User Space NameAddr (0,Hex)Access Na

Page 6

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 14 of 4630 70 RDI0RI B0 RW F031 71 RDI0SYN B1 RW F132 ACE00CR1 72 RW RDI0IS B2 RW

Page 7

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 15 of 461C 5C 9C DC1D 5D 9D OSC_GO_EN DD RW1E 5E 9E OSC_CR4 DE RW1F 5F 9F OSC_CR3

Page 8

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 16 of 46Electrical SpecificationsThis section presents the DC and AC electrical s

Page 9

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 17 of 46Operating Temperature DC Electrical Characteristics DC Chip-Level Specif

Page 10 - CY8C21123/CY8C21223/CY8C21323

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 18 of 46DC GPIO SpecificationsTable 13 lists the guaranteed maximum and minimum s

Page 11

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 19 of 46DC Amplifier SpecificationsThe following tables list the guaranteed maxim

Page 12

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 2 of 46ContentsPSoC Functional Overview ...

Page 13

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 20 of 46DC Switch Mode Pump SpecificationsTable 18 lists the guaranteed maximum a

Page 14

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 21 of 46Figure 12. Basic Switch Mode Pump CircuitDC POR and LVD SpecificationsTa

Page 15

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 22 of 46DC Programming SpecificationsTable 20 lists the guaranteed maximum and mi

Page 16

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 23 of 46AC Electrical CharacteristicsAC Chip-Level SpecificationsTable 22 lists t

Page 17

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 24 of 46 Table 23. 2.7-V AC Chip-Level SpecificationsSymbol Description Min Typ

Page 18

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 25 of 46AC General Purpose I/O SpecificationsTable 24 lists the guaranteed maximu

Page 19

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 26 of 46AC Digital Block SpecificationsTable 28 lists the guaranteed maximum and

Page 20 - = 10 mF capacitor, D

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 27 of 46Table 29. 2.7-V AC Digital Block SpecificationsFunction Description Min

Page 21

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 28 of 46AC External Clock SpecificationsThe following tables list the guaranteed

Page 22

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 29 of 46AC Programming SpecificationsTable 33 lists the guaranteed maximum and mi

Page 23

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 3 of 46PSoC Functional OverviewThe PSoC family consists of many programmable syst

Page 24

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 30 of 46Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus T

Page 25

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 31 of 46Packaging InformationThis section illustrates the packaging specification

Page 26

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 32 of 46Figure 16. 16-Pin (150-Mil) SOICFigure 17. 16-Pin QFN with no E-Pad 51-

Page 27

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 33 of 46Figure 18. 20-Pin (210-Mil) SSOPFigure 19. 24-Pin (4 × 4) QFN Important

Page 28

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 34 of 46Thermal Impedances Solder Reflow SpecificationsTable 37 shows the solder

Page 29

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 35 of 46Ordering InformationThe following table lists the CY8C21x23 PSoC device’s

Page 30

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 36 of 46AcronymsAcronyms UsedTable 39 lists the acronyms that are used in this do

Page 31 - 51-85066 *F

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 37 of 46Document ConventionsUnits of MeasureTable 40 lists the units of measures.

Page 32 - 001-09116 *J

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 38 of 46bias 1. A systematic deviation of a value from a reference value.2. The

Page 33 - 51-85203 *D

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 39 of 46digital-to-analog (DAC)A device that changes a digital signal to an analo

Page 34

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 4 of 46Analog SystemThe analog system consists of four configurable blocks to all

Page 35

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 40 of 46master device A device that controls the timing for data exchanges betwe

Page 36

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 41 of 46serial 1. Pertaining to a process in which all events occur one after th

Page 37

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 42 of 46ErrataThis section describes the errata for the CY8C21x23 PSoC® programma

Page 38

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 43 of 461. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extr

Page 39

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 44 of 46Document History PageDocument Title: CY8C21123/CY8C21223/CY8C21323, PSoC®

Page 40

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 45 of 46*P 3044869 NJF 10/01/2010 Added PSoC Device Characteristics table.Added D

Page 41

Document Number: 38-12022 Rev. *Y Revised August 20, 2014 Page 46 of 46PSoC Designer is a trademark and PSoC is a registered trademark of Cypress Sem

Page 42

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 5 of 46PSoC Device CharacteristicsDepending on your PSoC device characteristics,

Page 43

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 6 of 46Development Tool SelectionSoftwarePSoC DesignerAt the core of the PSoC dev

Page 44

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 7 of 46Designing with PSoC DesignerThe development process for the PSoC device di

Page 45

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 8 of 46Pin InformationThis section describes, lists, and illustrates the CY8C21x2

Page 46

CY8C21123/CY8C21223/CY8C21323Document Number: 38-12022 Rev. *Y Page 9 of 46Table 4. Pin Definitions – CY8C21223 16-Pin QFN with no E-Pad[3] Pin No.T

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