Cypress Semiconductor CY7C1527AV18 User Manual download pdf

72-Mbit DDR-II SRAM 2-Word

Burst Architecture

CY7C1516AV18, CY7C1527AV18

CY7C1518AV18, CY7C1520AV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-06982 Rev. *C Revised September 27, 2007

Features

■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 300 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ DDR-II operates with 1.5 cycle read latency when Delay Lock

Loop (DLL) is enabled

■ Operates as a DDR-I device with 1 cycle read latency in DLL

off mode

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

)

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1516AV18 – 8M x 8

CY7C1527AV18 – 8M x 9

CY7C1518AV18 – 4M x 18

CY7C1520AV18 – 2M x 36

Functional Description

The CY7C1516AV18, CY7C1527AV18, CY7C1518AV18, and

CY7C1520AV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a 1-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K

. Read data is

driven on the rising edges of C and C

if provided, or on the rising

edge of K and K

if C/C are not provided. Each address location

is associated with two 8-bit words in the case of CY7C1516AV18

and two 9-bit words in the case of CY7C1527AV18 that burst

sequentially into or out of the device. The burst counter always

starts with a “0” internally in the case of CY7C1516AV18 and

CY7C1527AV18. On CY7C1518AV18 and CY7C1520AV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1518AV18 and two 36-bit words in the case of

CY7C1520AV18 sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ

, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz

Maximum Operating Current x8 900 860 800 700 650 mA

x9 900 860 800 700 650

x18 940 860 800 700 650

x36 1080 985 900 735 650

[+] Feedback

1 2 3 4 5 6 ... 29 30

Summary of Contents

Page 1 - Burst Architecture

72-Mbit DDR-II SRAM 2-WordBurst ArchitectureCY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Cypress Semiconductor Corporation • 198 Champion Court

Page 2

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 10 of 30Truth TableThe truth table for the CY7C1516AV18, C

Page 3

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 11 of 30Write Cycle DescriptionsThe write cycle descriptio

Page 4

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 12 of 30IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs

Page 5

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 13 of 30IDCODEThe IDCODE instruction loads a vendor-specif

Page 6

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 14 of 30TAP Controller State DiagramThe state diagram for

Page 7

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 15 of 30TAP Controller Block DiagramTAP Electrical Charact

Page 8

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 16 of 30TAP AC Switching Characteristics Over the Operatin

Page 9

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 17 of 30Identification Register Definitions Instruction Fi

Page 10 - CY7C1518AV18, CY7C1520AV18

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 18 of 30Boundary Scan Order Bit # Bump ID Bit # Bump ID Bi

Page 11

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 19 of 30Power Up Sequence in DDR-II SRAMDDR-II SRAMs must

Page 12

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 2 of 30Logic Block Diagram (CY7C1516AV18)Logic Block Diagr

Page 13

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 20 of 30Maximum RatingsExceeding maximum ratings may impai

Page 14

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 21 of 30IDD VDD Operating Supply VDD = Max,IOUT = 0 mA,f =

Page 15

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 22 of 30CapacitanceTested initially and after any design o

Page 16 - [+] Feedback

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 23 of 30Switching Characteristics Over the Operating Range

Page 17

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 24 of 30Output TimestCOtCHQVC/C Clock Rise (or K/K in sing

Page 18

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 25 of 30Switching WaveformsFigure 3. Read/Write/Deselect

Page 19 - Power Up Waveforms

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 26 of 30Ordering Information Not all of the speed, package

Page 20

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 27 of 30250 CY7C1516AV18-250BZC 51-85195 165-Ball Fine Pit

Page 21

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 28 of 30167 CY7C1516AV18-167BZC 51-85195 165-Ball Fine Pit

Page 22 - AC Test Loads and Waveforms

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 29 of 30Package DiagramFigure 4. 165-Ball FBGA (15 x 17 x

Page 23

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 3 of 30Logic Block Diagram (CY7C1518AV18)Logic Block Diagr

Page 24

Document Number: 001-06982 Rev. *C Revised September 27, 2007 Page 30 of 30QDR RAMs and Quad Data Rate RAMs comprise a new family of products develope

Page 25

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 4 of 30Pin Configuration The pin configuration for CY7C151

Page 26

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 5 of 30CY7C1518AV18 (4M x 18)1234567891011A CQAAR/WBWS1K N

Page 27

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 6 of 30Pin Definitions Pin Name IO Pin DescriptionDQ[x:0]I

Page 28

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 7 of 30CQ Output Clock CQ Referenced with Respect to C. Th

Page 29 - Package Diagram

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 8 of 30Functional OverviewThe CY7C1516AV18, CY7C1527AV18,

Page 30 - Document History Page

CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18Document Number: 001-06982 Rev. *C Page 9 of 30current data. The SRAM does this by bypassing the m

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Cypress Semiconductor CY7C1527AV18 User Manual

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