Cypress Semiconductor CY7C1527AV18 User Manual download pdf (Page 25)

CY7C1516AV18, CY7C1527AV18

CY7C1518AV18, CY7C1520AV18

Document Number: 001-06982 Rev. *C Page 25 of 30

Switching Waveforms

Figure 3. Read/Write/Deselect Sequence

[26, 27, 28]

READ READREAD NOP NOP WRITEWRITE

NOP

2345678910

Q40

KHCH

DON’T CARE

UNDEFINED

CLZ

DOH

CHZ

KHKH

CYC

D20

D21 D30

D31

Q00 Q11Q01 Q10

Q41

CCQO

CQOH

CCQO

CQOH

CYC

R/W

CQ#

KHKH

CQD

CQDOH

CQH

CQHCQH

Notes

26. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

27. Outputs are disabled (High-Z) one clock cycle after a NOP.

28. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.

[+] Feedback

1 2 ... 20 21 22 23 24 25 26 27 28 29 30

72-Mbit DDR-II SRAM 2-Word 1
Burst Architecture 1
CY7C1516AV18, CY7C1527AV18 10
CY7C1518AV18, CY7C1520AV18 10
[+] Feedback 16
Power Up Waveforms 19
Capacitance 22
Thermal Resistance 22
AC Test Loads and Waveforms 22
Package Diagram 29
Document History Page 30

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