Cypress Semiconductor CY7C1511V18 User Manual download pdf

72-Mbit QDR™-II SRAM 4-Word

Burst Architecture

CY7C1511V18, CY7C1526V18

CY7C1513V18, CY7C1515V18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-05363 Rev. *F Revised August 06, 2008

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 300 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency, providing most current data

■ Core V

= 1.8 (± 0.1V); IO V

DDQ

= 1.4V to V

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1511V18 – 8M x 8

CY7C1526V18 – 8M x 9

CY7C1513V18 – 4M x 18

CY7C1515V18 – 2M x 36

Functional Description

The CY7C1511V18, CY7C1526V18, CY7C1513V18, and

CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR™-II architecture. QDR-II architecture

consists of two separate ports: the read port and the write port to

access the memory array. The read port has dedicated data

outputs to support read operations and the write port has

dedicated data inputs to support write operations. QDR-II archi-

tecture has separate data inputs and data outputs to completely

eliminate the need to “turn-around” the data bus that exists with

common IO devices. Each port can be accessed through a

common address bus. Addresses for read and write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR-II read and write ports are completely

independent of one another. To maximize data throughput, both

read and write ports are equipped with DDR interfaces. Each

address location is associated with four 8-bit words

(CY7C1511V18), 9-bit words (CY7C1526V18), 18-bit words

(CY7C1513V18), or 36-bit words (CY7C1515V18) that burst

sequentially into or out of the device. Because data can be trans-

ferred into and out of the device on every rising edge of both input

clocks (K and K

and C and C), memory bandwidth is maximized

while simplifying system design by eliminating bus

“turn-arounds”.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz

Maximum Operating Current x8 930 865 790 655 570 mA

x9 940 870 795 660 575

x18 1020 950 865 715 615

x36 1230 1140 1040 850 725

[+] Feedback

1 2 3 4 5 6 ... 31 32

Summary of Contents

Page 1 - Burst Architecture

72-Mbit QDR™-II SRAM 4-WordBurst ArchitectureCY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Cypress Semiconductor Corporation • 198 Champion Court •

Page 2

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 10 of 32Application ExampleFigure 1 shows four QDR-II used in a

Page 3

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 11 of 32Write Cycle Descriptions The write cycle description ta

Page 4

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 12 of 32Write Cycle DescriptionsThe write cycle description tab

Page 5

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 13 of 32IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs inco

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CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 14 of 32IDCODEThe IDCODE instruction loads a vendor-specific, 3

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CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 15 of 32TAP Controller State DiagramThe state diagram for the T

Page 8

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 16 of 32TAP Controller Block DiagramTAP Electrical Characterist

Page 9

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 17 of 32TAP AC Switching Characteristics Over the Operating Ran

Page 10 - Truth Table

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 18 of 32Identification Register Definitions Instruction FieldVa

Page 11 - CY7C1513V18, CY7C1515V18

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 19 of 32Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # B

Page 12

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 2 of 32Logic Block Diagram (CY7C1511V18)Logic Block Diagram (CY

Page 13

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 20 of 32Power Up Sequence in QDR-II SRAMQDR-II SRAMs must be po

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CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 21 of 32Maximum RatingsExceeding maximum ratings may impair the

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CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 22 of 32IDD [21]VDD Operating Supply VDD = Max,IOUT = 0 mA,f =

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CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 23 of 32CapacitanceTested initially and after any design or pro

Page 17 - [+] Feedback

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 24 of 32Switching Characteristics Over the Operating Range [22,

Page 18

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 25 of 32Output TimestCOtCHQVC/C Clock Rise (or K/K in single cl

Page 19

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 26 of 32Switching WaveformsFigure 5. Read/Write/Deselect Seque

Page 20 - DLL Constraints

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 27 of 32Ordering Information Not all of the speed, package and

Page 21 - Operating Range

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 28 of 32250 CY7C1511V18-250BZC 51-85195 165-Ball Fine Pitch Bal

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CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 29 of 32167 CY7C1511V18-167BZC 51-85195 165-Ball Fine Pitch Bal

Page 23 - Thermal Resistance

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 3 of 32Logic Block Diagram (CY7C1513V18)Logic Block Diagram (CY

Page 24

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 30 of 32Package DiagramFigure 6. 165-ball FBGA (15 x 17 x 1.4 m

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CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 31 of 32Document History PageDocument Title: CY7C1511V18/CY7C15

Page 26 - Switching Waveforms

Document Number: 38-05363 Rev. *F Revised August 06, 2008 Page 32 of 32QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by

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CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 4 of 32Pin Configuration The pin configuration for CY7C1511V18,

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CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 5 of 32CY7C1513V18 (4M x 18)1 2 3 4 5 6 7 8 9 10 11A CQVSS/144M

Page 29

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 6 of 32Pin Definitions Pin Name IO Pin DescriptionD[x:0]Input-S

Page 30 - Package Diagram

CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 7 of 32CQ Echo Clock CQ Referenced with Respect to C. This is a

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CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 8 of 32Functional OverviewThe CY7C1511V18, CY7C1526V18, CY7C151

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CY7C1511V18, CY7C1526V18CY7C1513V18, CY7C1515V18Document Number: 38-05363 Rev. *F Page 9 of 32Concurrent TransactionsThe read and write ports on the C

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Summary of Contents

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