Cypress Semiconductor CY7C1441AV33 User Manual download pdf (Page 24)

CY7C1441AV33

CY7C1443AV33

CY7C1447AV33

Document #: 38-05357 Rev. *F Page 23 of 31

Write Cycle Timing

[25, 26]

Note:

26.

Full width write can be initiated by either GW

LOW; or by GW HIGH, BWE LOW and BW

LOW.

Timing Diagrams (continued)

CYC

CLK

ADH

ADS

ADDRESS

CEH

CES

High-Z

BURST READ BURST WRITE

D(A2)

D(A2 + 1)

D(A1)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

ADH

ADS

ADH

ADS

OEHZ

ADVH

ADVS

WEH

WES

WEH

WES

Byte write signals are ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

ADSP

ADSC

BWE,

ADV

Data in (D)

ata Out (Q)

[+] Feedback

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Jameco Part Number 1412218 1
Flow-Through SRAM 2
CY7C1441AV33 10
CY7C1443AV33 10
CY7C1447AV33 10
3.3V TAP AC Test Conditions 16
2.5V TAP AC Test Conditions 16
Over the Operating Range 20
Thermal Resistance 21
AC Test Loads and Waveforms 21
Capacitance 21
Timing Diagrams 23
Timing Diagrams (continued) 24

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Cypress Semiconductor CY7C1441AV33 User Manual Page 24

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