Cypress Semiconductor SL811HS Specifications download pdf (Page 9)

SL811HS

Document #: 38-08008 Rev. *A Page 9 of 29

The registers in the SL811HS are divided into two major groups. The first group is referred to as USB Control registers. These

registers enable and provide status for control of USB transactions and data flow. The second group of registers provides control

and status for all other operations.

5.1 Register Values on Power-up and Reset

The following registers initialize to zero on power-up and reset:

• USB-A/USB-B Host Control Register [00H, 08H] bit 0 only

• Control Register 1 [05H]

• USB Address Register [07H]

• Current Data Set/Hardware Revision/SOF Counter LOW Register [0EH]

All other registers power-up and reset in an unknown state and should be initialized by firmware.

5.2 USB Control Registers

Communication and data flow on the USB uses the SL811HS’s USB A-B Control Registers. The SL811HS can communicate with

any USB Device functions and any specific endpoints via the USBA or USBB register sets.

The USB A-B Host Control Registers can be used in a Ping-Pong arrangement to manage traffic on the USB. The USB Host

Control Register also provides a means to interrupt an external CPU or Micro Controller when one of the USB protocol transac-

tions is completed. The table above shows the two sets of USB Host Control Registers, the “A” set and “B” set. The two register

sets allow for overlapped operation. When one set of parameters is being set up, the other is transferring. On completion of a

transfer to an endpoint, the next operation will be controlled by the other register set.

Note. On the SL11H, the USB-B set control registers are not used. The USB-B register set can be used only when SL811HS

mode is enabled by initializing register 0FH.

The SL811HS USB Host Control has two groups of five registers each, which map in the SL811HS memory space. These registers

are defined in the following tables.

SL11H (hex)

Address

SL811HS (hex)

Address

USB-A Host Control Register 00H 00H

USB-A Host Base Address 01H 01H

USB-A Host Base Length 02H 02H

USB-A Host PID, Device Endpoint (Write)/USB Status (Read) 03H 03H

USB-A Host Device Address (Write)/Transfer Count (Read) 04H 04H

Control Register1 05H 05H

Interrupt Enable Register 06H 06 H

Reserved Register Reserved Reserved

USB-B Host Control Register Reserved 08H

USB-B Host Base Address Reserved 09H

USB-B Host Base Length Reserved 0AH

USB-B Host PID, Device Endpoint (Write)/USB Status (Read) Reserved 0BH

USB-B Host Device Address (Write)/Transfer Count (Read) Reserved 0CH

Status Register 0DH 0DH

SOF Counter LOW (Write)/HW Revision Register (Read) 0EH 0E H

SOF Counter HIGH and Control Register2 Reserved 0F H

Memory Buffer 10H-FFH 10H-FFH

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 28 29

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Cypress Semiconductor SL811HS Specifications Page 9

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