Cypress Semiconductor NoBL CY7C1462AV25 User Manual

CY7C1460AV25CY7C1462AV2536-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ ArchitectureCypress Semiconductor Corporation • 198 Champion Court • San

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 10 of 31Partial Write Cycle DescriptionThe partial write cycle description table for C

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 11 of 31Partial Write Cycle DescriptionThe partial write cycle description table for C

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 12 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1460AV25/CY7C1462AV25 incorpora

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 13 of 31TDO. During this state, instructions are shifted through theinstruction regist

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 14 of 31TAP Controller State DiagramThe 0/1 next to each state represents the value of

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 15 of 31TAP Controller Block DiagramTAP TimingBypass Register0Instruction Register012I

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 16 of 31TAP AC Switching CharacteristicsOver the Operating RangeParameter [16, 17]Desc

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 17 of 312.5 V TAP AC Test ConditionsInput pulse levels ...

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 18 of 31Identification Register DefinitionsInstruction FieldCY7C1460AV25(1 M × 36)CY7C

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 19 of 31Boundary Scan Order165-ball FBGA [19]CY7C1460AV25 (1 M × 36), CY7C1462AV25 (2

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 2 of 31Logic Block Diagram – CY7C1462AV25A0, A1, ACMODEBWaBWbWECE1CE2CE3OEREAD LOGICDQ

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 20 of 31Maximum RatingsExceeding maximum ratings may impair the useful life of thedevi

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 21 of 31ISB3Automatic CE power-down current – CMOS inputsMax VDD, device deselected, V

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 22 of 31Switching CharacteristicsOver the Operating RangeParameter [23, 24]Description

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 23 of 31Switching WaveformsFigure 4. Read/Write/Timing [29, 30, 31]Figure 5. NOP, ST

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 24 of 31Figure 6. ZZ Mode Timing [33, 34]Switching Waveforms (continued)tZZISUPPLYCLK

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 25 of 31Ordering Code DefinitionsOrdering InformationCypress offers other versions of

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 26 of 31Package DiagramsFigure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outl

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 27 of 31Figure 8. 165-ball FBGA (15 × 17 × 1.4 mm) (0.45 Ball Diameter) Package Outli

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 28 of 31Acronyms Document ConventionsUnits of MeasureAcronym DescriptionCEchip enableC

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 29 of 31Document History PageDocument Title: CY7C1460AV25/CY7C1462AV25, 36-Mbit (1 M ×

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 3 of 31ContentsSelection Guide ...

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 30 of 31*D 473650 See ECN VKN Updated Maximum Ratings (Added the Maximum Rating for Su

Document Number: 38-05354 Rev. *J Revised September 24, 2012 Page 31 of 31ZBT is a registered trademark of Integrated Device Technology, Inc. No Bus

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 4 of 31Selection GuideDescription 250 MHz 200 MHz 167 MHz UnitMaximum access time 2.6

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 5 of 31Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinoutPin Configurations (continued

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 6 of 31Pin DefinitionsPin Name I/O Type Pin DescriptionA0, A1, A Input-synchronousAddr

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 7 of 31Functional OverviewThe CY7C1460AV25/CY7C1462AV25 aresynchronous-pipelined burst

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 8 of 31On the next clock rise the data presented to DQ and DQP(DQa,b,c,d/DQPa,b,c,d fo

CY7C1460AV25CY7C1462AV25Document Number: 38-05354 Rev. *J Page 9 of 31Truth TableThe truth table for CY7C1460AV25/CY7C1462AV25 follows. [1, 2, 3, 4,