Cypress Semiconductor FX2LP Datasheet

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016AEZ-USB® FX2LP™ USB Microcontroller High-Speed USB Peripheral ControllerCypress Semiconductor Corporation

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 10 of 66Figure 2-4. External Code Memory, EA = 12.11 Register Addres

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 11 of 662.12 Endpoint RAM2.12.1 Size 3 × 64 bytes (Endpoints 0 and

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 12 of 662.12.5 Default Full Speed Alternate Settings 2.12.6 Default

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 13 of 662.13.3 GPIF and FIFO Clock RatesAn 8051 register bit selects

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 14 of 662.18 I2C ControllerFX2LP has one I2C port that is driven by t

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 15 of 663. Pin AssignmentsFigure 3-1 on page 16 identifies all signal

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 16 of 66Figure 3-1. SignalRDY0RDY1CTL0CTL1CTL2INT0#/PA0INT1#/PA1PA2WU

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 17 of 66Figure 3-2. CY7C68013A/CY7C68014A 128-Pin TQFP Pin Assignment

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 18 of 66Figure 3-3. CY7C68013A/CY7C68014A 100-Pin TQFP Pin Assignment

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 19 of 66Figure 3-4. CY7C68013A/CY7C68014A 56-Pin SSOP Pin Assignment1

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 2 of 66 Cypress’s EZ-USB® FX2LP (CY7C68013A/14A) is a low power versi

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 20 of 66Figure 3-5. CY7C68013A/14A/15A/16A 56-Pin QFN Pin Assignment2

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 21 of 66Figure 3-6. CY7C68013A 56-pin VFBGA Pin Assignment – Top View

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 22 of 663.1 CY7C68013A/15A Pin DescriptionsThe FX2LP pin descriptions

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 23 of 6634 28 – – BKPT Output L Breakpoint. This pin goes active (HIGH

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 24 of 6685 70 43 36 7F PA3 or WU2I/O/Z I(PA3)Multiplexed pin whose fun

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 25 of 6655 45 30 23 5G PB5 orFD[5]I/O/Z I(PB5)Multiplexed pin whose fu

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 26 of 66104 82 54 47 6B PD2 orFD[10]I/O/Z I(PD2)Multiplexed pin whose

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 27 of 66112 90 – – – PE4 orRXD1OUTI/O/Z I(PE4)Multiplexed pin whose fu

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 28 of 6670 55 37 30 7G CTL1 orFLAGBO/Z H Multiplexed pin whose functio

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 29 of 6650 40 – – – TXD0 Output H TXD0 is the active-HIGH TXD0 output

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 3 of 66ContentsApplications ...

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 30 of 664. Register SummaryFX2LP register bit definitions are describ

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 31 of 66E62B 1 ECC1B1 ECC1 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 32 of 66E65D 1 USBIRQ[12]USB Interrupt Requests 0 EP0ACK HSGRANT URES

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 33 of 66E6A0 1 EP0CS Endpoint 0 Control and Sta-tusHSNAK 0 0 0 0 0 BUS

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 34 of 66E6CF 1 GPIFTCB2[11]GPIF Transaction Count Byte 2TC23 TC22 TC21

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 35 of 66xxxx I²C Configuration Byte 0 DISCON 0 0 0 0 0 400KHZ xxxxxxxx

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 36 of 66BE 1 GPIFSGLDATLX[13]GPIF Data L w/ Trigger D7 D6 D5 D4 D3 D2

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 37 of 665. Absolute Maximum RatingsExceeding maximum ratings may shor

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 38 of 668. DC Characteristics 8.1 USB TransceiverUSB 2.0 compliant i

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 39 of 669. AC Electrical Characteristics9.1 USB TransceiverUSB 2.0 c

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 4 of 661. Applications Portable video recorder MPEG/TV conversion

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 40 of 669.3 Data Memory Read Figure 9-2. Data Memory Read Timing Dia

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 41 of 669.4 Data Memory WriteFigure 9-3. Data Memory Write Timing Di

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 42 of 669.5 PORTC Strobe Feature TimingsThe RD# and WR# are present i

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 43 of 669.6 GPIF Synchronous SignalsFigure 9-6. GPIF Synchronous Sig

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 44 of 669.1 Slave FIFO Synchronous ReadFigure 9-7. Slave FIFO Synchr

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 45 of 669.8 Slave FIFO Asynchronous ReadFigure 9-8. Slave FIFO Async

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 46 of 669.9 Slave FIFO Synchronous WriteFigure 9-9. Slave FIFO Synch

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 47 of 669.10 Slave FIFO Asynchronous WriteFigure 9-10. Slave FIFO As

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 48 of 66There is no specific timing requirement that should be met for

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 49 of 669.13 Slave FIFO Output EnableFigure 9-14. Slave FIFO Output

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 5 of 662.5 USB Boot MethodsDuring the power up sequence, internal log

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 50 of 669.16 Slave FIFO Asynchronous AddressFigure 9-17. Slave FIFO

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 51 of 66Figure 9-18 on page 50 shows the timing relationship of the SL

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 52 of 66Figure 9-20 shows the timing relationship of the SLAVE FIFO si

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 53 of 669.17.3 Sequence Diagram of a Single and Burst Asynchronous Re

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 54 of 669.17.4 Sequence Diagram of a Single and Burst Asynchronous Wr

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 55 of 6610. Ordering InformationOrdering Code DefinitionsTable 32. O

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 56 of 6611. Package DiagramsThe FX2LP is available in five packages:

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 57 of 66Figure 11-2. 56-Pin QFN 8 × 8 mm Sawn Version (001-53450)001-

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 58 of 66Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 59 of 66Figure 11-4. 128-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 6 of 66The FX2LP jump instruction is encoded as follows:If Autovectori

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 60 of 66Figure 11-5. 56-Pin VFBGA (5 × 5 × 1.0 mm) 0.50 Pitch, 0.30 B

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 61 of 6612. PCB Layout RecommendationsFollow these recommendations to

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 62 of 6613. Quad Flat Package No Leads (QFN) Package Design NotesElec

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 63 of 66Acronyms Document ConventionsUnits of MeasureAcronyms Used in

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 64 of 66Document History Page Document Title: CY7C68013A, CY7C68014A,

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 65 of 66*L 2064406 CMCC/PYRSSee ECN Changed TID numberRemoved T0OUT an

Document #: 38-08032 Rev. *V Revised February 7, 2012 Page 66 of 66>FX2LP is a trademark and EZ-USB is a registered trademark of Cypress Semicondu

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 7 of 66If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP registe

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 8 of 66 2.9.2 Wakeup PinsThe 8051 puts itself and the rest of the ch

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016ADocument #: 38-08032 Rev. *V Page 9 of 66Figure 2-3. Internal Code Memory, EA = 0Inside FX2LP Outside F