CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. AH Page 59 of 64
17. Errata
This section describes the errata for the CY8C24x94 device. Details include errata trigger conditions, scope of impact, available
workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
CY8C24x94 Errata Summary
The following table defines the errata applicability to available devices.
1. The DP line of the USB interface may pulse low when the PSoC device wakes from sleep causing an unexpected wake-up
of the host computer.
■ PROBLEM DEFINITION
When the device is operating at 4.75 V to 5.25 V and the 3.3 V regulator is enabled, a short low pulse may be created on the DP
signal line during device wake-up. The 15-20 µs low pulse of the DP line may be interpreted by the host computer as a deattach or
the beginning of a wake-up.
■ TRIGGER CONDITION(S)
The bandgap reference voltage used by the 3.3 V regulator decreases during sleep due to leakage. Upon device wake up, the bandgap
is reenabled and after a delay for settling, the 3.3 V regulator is enabled. On some devices the 3.3 V regulator that is used to generate
the USB DP signal may be enabled before the bandgap is fully stabilized. This can cause a low pulse on the regulator output and DP
signal line until the bandgap stabilizes. In applications where Vdd is 3.3 V, the regulator is not used and therefore the DP low pulse
is not generated.
■ WORKAROUND
To prevent the DP signal from pulsing low, keep the bandgap enabled during sleep. The most efficient method is to set the No Buzz
bit in the OSC_CR0 register. The No Buzz bit keeps the bandgap powered and output stable during sleep. Setting the No Buzz bit
results in nominal 100 µA increase to sleep current. Leaving the analog reference block enabled during sleep also resolves this issue
because it forces the bandgap to remain enabled. An example for disabling the No Buzz bit is listed below.
Assembly
M8C_SetBank1
or reg[OSC_CR0], 0x20
M8C_SetBank0
C
OSC_CR0 |= 0x20;
2. Invalid Flash reads may occur if Vdd is pulled to -0.5 V just before power on
■ PROBLEM DEFINITION
When Vdd of the device is pulled below ground just before power on, the first read from each 8K Flash page may be corrupted. This
issue does not affect Flash page 0 because it is the selected page upon reset.
■ TRIGGER CONDITION(S)
When Vdd is pulled below ground before power on, an internal Flash reference may deviate from its nominal voltage. The reference
deviation tends to result in the first Flash read from that page returning 0xFF. During the first read from each page, the reference is
reset resulting in all future reads returning the correct value. A short delay of 5 µs before the first real read provides time for the
reference voltage to stabilize.
Part Number
CY8C24x94
Items Part Number
1. The DP line of the USB interface may pulse low when the PSoC device wakes from sleep causing an
unexpected wake-up of the host computer.
CY8C24x94
2. Invalid Flash reads may occur if Vdd is pulled to -0.5 V just before power on CY8C24x94
3. PMA Index Register fails to auto-increment with CPU_Clock set to SysClk/1 (24 MHz). CY8C24x94
(64 pages)
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