Cypress Semiconductor CY7C1543V18 Datasheet

THIS SPEC IS OBSOLETESpec No: 001-05389Spec Title: CY7C1543V18/CY7C1545V18, 72-MBIT QDR (R) II+ SRAM 4-WORD BURST ARCHITECTURE

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 9 of 26Truth TableThe truth table for CY7C1543V18 and CY7C1545V18 follows.[3, 4, 5, 6, 7

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 10 of 26Write Cycle DescriptionsThe write cycle description table for CY7C1545V18 follow

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 11 of 26IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs incorporate a serial boundary

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 12 of 26IDCODEThe IDCODE instruction loads a vendor-specific, 32-bit code intothe instru

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 13 of 26TAP Controller State DiagramThe state diagram for the TAP controller follows.[12

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 14 of 26TAP Controller Block DiagramTAP Electrical Characteristics Over the Operating Ra

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 15 of 26TAP AC Switching Characteristics Over the Operating Range [16, 17]Parameter Desc

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 16 of 26Identification Register Definitions Instruction FieldValueDescriptionCY7C1543V18

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 17 of 26Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID0 6R

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 18 of 26Power Up Sequence in QDR II+ SRAMQDR II+ SRAMs must be powered up and initialize

72-Mbit QDR® II+ SRAM 4-Word BurstArchitecture (2.0 Cycle Read Latency)CY7C1543V18CY7C1545V18Cypress Semiconductor Corporation • 198 Champion Court •

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 19 of 26Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 20 of 26IDD [22]VDD Operating Supply VDD = Max, IOUT = 0 mA,f = fMAX = 1/tCYC375 MHz x18

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 21 of 26CapacitanceTested initially and after any design or process change that may affe

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 22 of 26Switching Characteristics Over the Operating Range [23, 24]CYParameterConsortium

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 23 of 26Switching WaveformsRead/Write/Deselect Sequence Figure 5. Waveform for 2.0 Cycl

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 24 of 26Ordering Information The following table contains only the parts that are curren

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 25 of 26Document History PageDocument Title: CY7C1543V18/CY7C1545V18, 72-Mbit QDR® II+ S

Document Number: 001-05389 Rev. *H Revised October 12, 2010 Page 26 of 26QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 2 of 26ContentsFeatures ...

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 3 of 26Logic Block Diagram (CY7C1543V18)Logic Block Diagram (CY7C1545V18)1M x 18 ArrayCL

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 4 of 26Pin Configuration The pin configuration for CY7C1543V18 and CY7C1545V18 follow.[2

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 5 of 26Pin Definitions Pin Name I/O Pin DescriptionD[x:0]Input-SynchronousData Input Sig

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 6 of 26TMS Input TMS Pin for JTAG.NC N/A Not Connected to the Die. Can be tied to any vo

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 7 of 26Functional OverviewThe CY7C1543V18 and CY7C1545V18 are synchronouspipelined burst

CY7C1543V18CY7C1545V18Document Number: 001-05389 Rev. *H Page 8 of 26Depth ExpansionThe CY7C1543V18 has a port select input for each port. Thisenables