Cypress Semiconductor CY7C1314BV18 Datasheet download pdf

18 Mbit QDR

II SRAM Two Word Burst

Architecture

CY7C1312BV18

CY7C1314BV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05619 Rev. *G Revised August 25, 2009

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 250 MHz clock for high bandwidth

■ 2-word burst on all accesses

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 500 MHz) at 250 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self timed writes

■ Available in x18, and x36 configurations

■ Full data coherency, providing most current data

■ Core V

= 1.8V (±0.1V); IO V

DDQ

= 1.4V to V

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1312BV18 – 1M x 18

CY7C1314BV18 – 512K x 36

Functional Description

The CY7C1312BV18, and CY7C1314BV18 are 1.8V

Synchronous Pipelined SRAMs, equipped with QDR

II archi-

tecture. QDR II architecture consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. QDR II

architecture has separate data inputs and data outputs to

completely eliminate the need to “turn around” the data bus

required with common IO devices. Access to each port is accom-

plished through a common address bus. The read address is

latched on the rising edge of the K clock and the write address

is latched on the rising edge of the K

clock. Accesses to the QDR

II read and write ports are completely independent of one

another. To maximize data throughput, both read and write ports

are provided with DDR interfaces. Each address location is

associated with two 18 bit words (CY7C1312BV18), or 36 bit

words (CY7C1314BV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K

and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus “turn arounds”.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self timed write circuitry.

Selection Guide

Description 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 250 200 167 MHz

Maximum Operating Current x18 800 675 600 mA

x36 900 750 650

[+] Feedback

1 2 3 4 5 6 ... 26 27

Summary of Contents

Page 1 - Architecture

18 Mbit QDR® II SRAM Two Word BurstArchitectureCY7C1312BV18CY7C1314BV18Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-170

Page 2

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 10 of 27IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs incorporate a serial boundary sca

Page 3

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 11 of 27between the TDI and TDO pins and shifts the IDCODE out of thedevice when the TAP con

Page 4

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 12 of 27TAP Controller State DiagramThe state diagram for the TAP controller follows. [9]TES

Page 5

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 13 of 27TAP Electrical Characteristics Over the Operating Range [10, 11, 12]Parameter Descri

Page 6

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 14 of 27TAP AC Switching Characteristics Over the Operating Range [13, 14]Parameter Descript

Page 7

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 15 of 27Identification Register Definitions Instruction FieldValueDescriptionCY7C1312BV18 CY

Page 8

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 16 of 27Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID0 6R 27 1

Page 9

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 17 of 27Power Up Sequence in QDR II SRAMQDR II SRAMs must be powered up and initialized in a

Page 10 - CY7C1314BV18

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 18 of 27Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. Th

Page 11

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 19 of 27ISB1Automatic Power Down CurrentMax VDD, Both Ports Deselected, VIN ≥ VIH or VIN ≤ V

Page 12

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 2 of 27512K x 18 ArrayCLKA(18:0)Gen.KKControlLogicAddressRegisterD[17:0]Read Add. DecodeRead

Page 13

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 20 of 27CapacitanceTested initially and after any design or process change that may affect t

Page 14

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 21 of 27Switching Characteristics Over the Operating Range [20, 21]CypressParameterConsortiu

Page 15

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 22 of 27Switching Characteristics Over the Operating Range [20, 21] (continued)CypressParame

Page 16

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 23 of 27Switching WaveformsFigure 5. Read/Write/Deselect Sequence [25, 26, 27]K1234581067KR

Page 17

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 24 of 27Ordering InformationThe table below contains only the parts that are currently avail

Page 18

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 25 of 27Package DiagramFigure 6. 165-Ball FBGA (13 x 15 x 1.4 mm)51-85180 *B[+] Feedback

Page 19

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 26 of 27Document History PageDocument Title: CY7C1312BV18/CY7C1314BV18, 18 Mbit QDR® II SRAM

Page 20

Document #: 38-05619 Rev. *G Revised August 25, 2009 Page 27 of 27QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypr

Page 21

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 3 of 27Pin Configuration The pin configuration for CY7C1312BV18, and CY7C1314BV18 follow. [1

Page 22

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 4 of 27Pin Definitions Pin Name IO Pin DescriptionD[x:0]Input-SynchronousData Input Signals.

Page 23

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 5 of 27TDO Output TDO for JTAG.TCK Input TCK Pin for JTAG.TDI Input TDI Pin for JTAG.TMS Inp

Page 24

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 6 of 27Functional OverviewThe CY7C1312BV18, and CY7C1314BV18 are synchronouspipelined Burst

Page 25

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 7 of 27Echo ClocksEcho clocks are provided on the QDR II to simplify data captureon high spe

Page 26

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 8 of 27Truth TableThe truth table for CY7C1312BV18, and CY7C1314BV18 follows. [2, 3, 4, 5, 6

Page 27

CY7C1312BV18CY7C1314BV18Document #: 38-05619 Rev. *G Page 9 of 27Write Cycle DescriptionsThe write cycle description table for CY7C1314BV18 follows. [

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